• 센서학회지
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• 제29권1호
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• pp.14-18
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• 2020

This study investigates the nitrogen dioxide (NO₂) sensing characteristics of an Si MOSFET gas sensor with a tungsten trioxide (WO₃) sensing layer deposited using the sputtering method. The Si MOSFET gas sensor consists of a horizontal floating gate (FG) interdigitated with a control gate (CG). The WO₃ sensing layer is deposited on the interdigitated CG-FG of a field effect transistor(FET)-type gas sensor platform. The sensing layer is deposited with different thicknesses of the film ranging from 100 nm to 1 ㎛ by changing the deposition times during the sputtering process. The sensing characteristics of the fabricated gas sensor are measured at different NO₂ concentrations and operating temperatures. The response of the gas sensor increases as the NO₂ concentration and operating temperature increase. However, the gas sensor has an optimal performance at 180℃ considering both response and recovery speed. The response of the gas sensor increases significantly from 24% to 138% as the thickness of the sensing layer increases from 100 nm to 1 ㎛. The sputtered WO₃ film consists of a dense part and a porous part. As reported in previous work, the area of the porous part of the film increases as the thickness of the film increases. This increased porous part promotes the reaction of the sensing layer with the NO₂ gas. Consequently, the response of the gas sensor increases as the thickness of the sputtered WO₃ film increases.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.243-246
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• 2004

W CMP 공정에서 abrasive 의 size 및 shape 에 따른 CMP 거동에 대해 관찰하였으며, 주요 제거 막질인 W 막질과 stopping layer 로 사용되는 Oxide 막질에 대한 압력(P)과 상대 속도(V) 영향성을 관찰하였다. CMP 제거량이 입자의 size 변화에 의존한다는 기존의 이론과는 달리 응집도(aggregate ratio) 변화가 주요 변수임을 밝혀 내었다. 한편, 각 막질에 대한 P,V 영향성 평가를 통해, 변형된 Prestonian equation 이 abrasive size 및 shape 에 상관없이 W 막질의 제거 거동을 설명하는데 중요한 역할을 수행함을 보였다. 그렇지만, W CMP 공정에서 stopping layer 로 사용되는 oxide 막질의 거동을 설명하는 데에는 어려움이 있었으며, 특히 P,V 에 의한 비선형적 removal rate(RR) 거동발생으로 인해 기존의 이론치와는 많은 차이를 나타내었다. 또한, abrasive size 와 shape 에 따라서도 복잡한 거동을 나타낸다.

• 한국산학기술학회논문지
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• 제10권7호
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• pp.1489-1496
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• 2009

비정질 인듐-갈륨-아연 산화물 박막트랜지스터를 모델링 하여서, 능동층의 구조, 두께, 평형상태의 전자밀도에 대응하는 박막트랜지스터의 특성을 연구하였다. 단일 능동층 박막트랜지스터의 경우, 능동층이 얇을 때 높은 전계효과이동도를 보였다. 문턱전압의 절대값은 능동층의 두께가 20 nm일 때 최저치를 보였으며, 문턱전압이하 기울기는 두께에 대한 의존성을 보이지 않았다. 복층구조 능동층의 경우, 하부의 능동층이 높은 평형상태 전자밀도를 가질 때보다 우수한 스위칭 특성을 보였다. 이 경우에도 능동층의 두께가 얇을 때에 높은 전계효과 이동도를 보였다. 높은 평형상태 전자밀도의 능동층의 두께를 증가시키면 문턱전압은 음의 방향으로 이동하였다. 문턱전압이하 기울기는 능동층의 구조에 대하여 특별한 의존성을 보이지 않았다. 이상과 같은 데이터는 산화물반도체 박막트랜지스터 능동층의 구조, 두께, 도핑비율을 최적화함에 효과적으로 사용될 것으로 기대된다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.341-341
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• 2012

Recently, oxide semi-conductor materials have been investigated as promising candidates replacing a-Si:H and poly-Si semiconductor because they have some advantages of a room-temperature process, low-cost, high performance and various applications in flexible and transparent electronics. Particularly, amorphous indium-gallium-zinc-oxide (a-IGZO) is an interesting semiconductor material for use in flexible thin film transistor (TFT) fabrication due to the high carrier mobility and low deposition temperatures. In this work, we demonstrated improvement of flexibility in IGZO TFTs, which were fabricated on polyimide (PI) substrate. At first, a thin poly-4vinyl phenol (PVP) layer was spin coated on PI substrate for making a smooth surface up to 0.3 nm, which was required to form high quality active layer. Then, Ni gate electrode of 100 nm was deposited on the bare PVP layer by e-beam evaporator using a shadow mask. The PVP and $Al_2O_3$ layers with different thicknesses were used for organic/inorganic multi gate dielectric, which were formed by spin coater and atomic layer deposition (ALD), respectively, at $200^{\circ}C$. 70 nm IGZO semiconductor layer and 70 nm Al source/drain electrodes were respectively deposited by RF magnetron sputter and thermal evaporator using shadow masks. Then, IGZO layer was annealed on a hotplate at $200^{\circ}C$ for 1 hour. Standard electrical characteristics of transistors were measured by a semiconductor parameter analyzer at room temperature in the dark and performance of devices then was also evaluated under static and dynamic mechanical deformation. The IGZO TFTs incorporating hybrid gate dielectrics showed a high flexibility compared to the device with single structural gate dielectrics. The effects of mechanical deformation on the TFT characteristics will be discussed in detail.

• 전기전자학회논문지
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• 제25권3호
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• pp.467-472
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• 2021

고온에서도 반도체 소자의 안정적인 동작이 필요하다. 반도체 소자의 구조중에서 고온에서 불안정한 전기적 응답을 야기할 수 있는 영역은 금속과 반도체가 접합하는 콘택층이다. 본 연구에서는 p형 SiC 층위에 니켈-실리사이드(NiSix)의 콘택층을 형성하는 공정과정에 포함되는 어닐링 공정 조건이 콘택 저항의 비저항과 전체 저항에 미치는 효과를 고찰하였다. 이를 위해, 4인치 p형 SiC층 위에 전송길이 이론(transfer length method: TLM) 측정을 위한 알련의 전극 패턴들을 형성하였고, 어닐링 온도(1700와 1800℃)와 어닐링 시간(30와 60분)을 달리하여 4종의 시료를 제조하였으며, TLM을 이용한 저항을 측정하였다. 그 결과, 어닐링 조건이 콘택층의 저항과 소자의 전기적 안정성에 영향을 미치는 사실을 확인하였다.

• 한국재료학회지
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• 제19권4호
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• pp.207-211
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• 2009

In this study, we attempted to develop a convenient aluminizing process, using Al-Ti mixed slurry as an aluminum source, to control the Al content of the aluminized layer as a result of a one-step process and can be widely adopted for coating complex-shaped components. The aluminizing process was carried out by the heat treatment on disc and rod shaped S45C steel substrates with Al-Ti mixed slurries that were composed of various mixed ratios (wt%) of Al and Ti powders. The surface of the resultant aluminized layer was relatively smooth with no obvious cracks. The aluminized layers mainly contain an Fe-Al compound as the bulk phase. However, the Al concentration and the thickness of the aluminized layer gradually decrease as the Ti proportion among Al-Ti mixed slurries increases. It has also been shown that the Al-Ti compound layer, which formed on the substrate during heat treatment, easily separates from the substrate. In addition, the incorporation of Ti into the substrate surface during heat treatment was not observed.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회B
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• pp.2032-2037
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• 2007

Numerical analysis was conducted to investigate the atomic layer deposition(ALD) of silicon nitride using silane and ammonia as precursors. The present study simulated the surface reactions for as-deposited $Si_3N_4$ as well as the kinetics for the reactions of $SiH_4$ and $NH_3$on the semiconductor wafer. The present numerical results showed that the ALD process is dependent on the activation constant. It was also shown that the low activation constant leads to the self-limiting reaction required for the ALD process. The inlet and wafer temperatures were 473 K and 823 K, respectively. The system pressure is 2 Torr.

• 한국재료학회지
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• 제26권6호
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• pp.342-346
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• 2016

To observe the bonding structure and electrical characteristics of a GZO oxide semiconductor, GZO was deposited on ITO glasses and annealed at various temperatures. GZO was found to change from crystal to amorphous with increasing of the annealing temperatures; GZO annealed at $200^{\circ}C$ came to have an amorphous structure that depended on the decrement of the oxygen vacancies; increase the mobility due to the induction of diffusion currents occurred because of an increment of the depletion layer. The increasing of the annealing temperature caused a reduction of the carrier concentration and an increase of the bonding energy and the depletion layer; therefore, the large potential barrier increased the diffusion current dna the Hall mobility. However, annealing temperatures over $200^{\circ}C$ promoted crystallinity by the defects without oxygen vacancies, and then degraded the depletion layer, which became an Ohmic contact without a potential barrier. So the current increased because of the absence of a potential barrier.

• Journal of Electrical Engineering and Technology
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• 제6권2호
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• pp.233-238
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• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• KIEE International Transactions on Electrophysics and Applications
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• 제3C권2호
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• pp.66-69
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• 2003

Various semiconductor nanowires such as GaN, GaP, InP, Si$_3$N$_4$, SiO$_2$/Si, and SiC were coated conformally with aluminum oxide (Al$_2$O$_3$) layers by atomic layer deposition (ALD) using trimethylaluminum (TMA) and distilled water ($H_2O$) at a temperature of 20$0^{\circ}C$. Transmission electron microscopy (TEM) revealed that A1203 cylindrical shells conformally coat the semiconductor nanowires. This study suggests that the ALD of $Al_2$O$_3$ on nanowires is a promising method for preparing cylindrical dielectric shells for coaxially gated nanowire field-effect transistors.