• 제목/요약/키워드: Semiconductor layer

검색결과 1,405건 처리시간 0.03초

상부전극에 의한 염료감응형태양전지의 특성 (Properties of Dye-sensitized Solar Cell by Upper Electrodes)

  • 마재평
    • 반도체디스플레이기술학회지
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    • 제11권1호
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    • pp.41-47
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    • 2012
  • In DSSC, fundamental process conditions of upper electrode were established and low cost-oriented method for TCO layer was proposed. Especially, prominent properties, that is, open-circuit voltage of 500mV or more and short-circuit current of $25mA/cm^2$ were yielded by 2-step sintering of semiconductive powder layer. High efficiency-DSSC was able to fabricate without high cost-semiconductor apparatus in common laboratory conditions.

The strategy for the fabrication of oxide TFTs with excellent device stabilities: The novel oxide TFT

  • Jeong, Jae-Kyeong;Park, Jin-Seong;Mo, Yeon-Gon;Kim, Hye-Dong
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.1047-1050
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    • 2009
  • The two approaches to improve the stability of oxide TFTs are described. First approach is the optimization of device architecture including MIS structure and passivation layer using conventional InGaZnO semiconductor channel layer. Second approach is to develop the new kinds of oxide semiconductor materials, which is very robust and stable against the gate bias stress and thermal stress.

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Numerical Analysis of Pressure and Temperature Effects on Residual Layer Formation in Thermal Nanoimprint Lithography

  • Lee, Ki Yeon;Kim, Kug Weon
    • 반도체디스플레이기술학회지
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    • 제12권2호
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    • pp.93-98
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    • 2013
  • Nanoimprint lithography (NIL) is a next generation technology for fabrication of micrometer and nanometer scale patterns. There have been considerable attentions on NIL due to its potential abilities that enable cost-effective and high-throughput nanofabrication to the display device and semiconductor industry. To successfully imprint a nanosized pattern with the thermal NIL, the process conditions such as temperature and pressure should be appropriately selected. This starts with a clear understanding of polymer material behavior during the thermal NIL process. In this paper, a filling process of the polymer resist into nanometer scale cavities during the thermal NIL at the temperature range, where the polymer resist shows the viscoelastic behaviors with consideration of stress relaxation effect of the polymer. In the simulation, the filling process and the residual layer formation are numerically investigated. And the effects of pressure and temperature on NIL process, specially the residual layer formation are discussed.

각 층에 따른 염료감응형 태양전지의 특성 개선 - I (-상부전극을 중심으로) (An Improvemcent of the Characteristics of DSSC by Each Layers - I (- Upper Electrode))

  • 마재평;박치선
    • 반도체디스플레이기술학회지
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    • 제10권2호
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    • pp.57-63
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    • 2011
  • Photovoltaic effect is confirmed in DSSC fabricated under the common conditions. In upper electrodes, validity of ZnO as new TCO material was investigated and an improvement of characteristics in DSSC was tried by control of process conditions at semiconductive powder layer. ZnO thin film showed very high resistivity, therefore efficiency of solar cell was lower than that of conventional ITO-related material. DSSC characteristics was able to improve by thin blocking layer doposited between the TCO and semiconductor layer.

Stress Analysis in Cooling Process for Thermal Nanoimprint Lithography with Imprinting Temperature and Residual Layer Thickness of Polymer Resist

  • Kim, Nam Woong;Kim, Kug Weon
    • 반도체디스플레이기술학회지
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    • 제16권4호
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    • pp.68-74
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    • 2017
  • Nanoimprint lithography (NIL) is a next generation technology for fabrication of micrometer and nanometer scale patterns. There have been considerable attentions on NIL due to its potential abilities that enable cost-effective and high-throughput nanofabrication to the display device and semiconductor industry. Up to now there have been a lot of researches on thermal NIL, but most of them have been focused on polymer deformation in the molding process and there are very few studies on the cooling and demolding process. In this paper a cooling process of the polymer resist in thermal NIL is analyzed with finite element method. The modeling of cooling process for mold, polymer resist and substrate is developed. And the cooling process is numerically investigated with the effects of imprinting temperature and residual layer thickness of polymer resist on stress distribution of the polymer resist. The results show that the lower imprinting temperature, the higher the maximum von Mises stress and that the thicker the residual layer, the greater maximum von Mises stress.

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SiO2/Al2O3 적층 감지막의 두께 최적화를 통한 고성능 Electrolyte-insulator-semiconductor pH 센서의 제작 (Thickness Optimization of SiO2/Al2O3 Stacked Layer for High Performance pH Sensor Based on Electrolyte-insulator-semiconductor Structure)

  • 구자경;장현준;조원주
    • 한국전기전자재료학회논문지
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    • 제25권1호
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    • pp.33-36
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    • 2012
  • In this study, the thickness effects of $Al_2O_3$ layer on the sensing properties of $SiO_2/Al_2O_3$ (OA) stacked membrane were investigated using electrolyte-insulator-semiconductor (EIS) structure for high quality pH sensor. The $Al_2O_3$ layers with a respective thickness of 5 nm, 15 nm, 23 nm, 50 nm, and 100 nm were deposited on the 5-nm-thick $SiO_2$ layers. The electrical characteristics and sensing properties of each OA membranes were investigated using metal-insulator-semiconductor (MIS) and EIS devices, respectively. As a result, the OA stacked membrane with 23-nm-thick $Al_2O_3$ layer shows the excellent characteristics as a sensing membrane of EIS sensor, which can enhance the signal to noise ratio.

Pentacene-based Thin Film Transistors with Improved Mobility Characteristics using Hybrid Gate Insulator

  • Park, Chang-Bum;Jung, Keum-Dong;Jin, Sung-Hun;Park, Byung-Gook;Lee, Jong-Duk
    • Journal of Information Display
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    • 제6권2호
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    • pp.16-18
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    • 2005
  • Hybrid insulator pentacene thin film transistors (TFTs) are fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layer on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility is increased to more than 35 times than that of the TFT which has only a gate insulator of $SiO_2$ at the same electric field. The carrier mobility of $1.80cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}/I_{off}$ current ratio> $1.10{\times}10^5$ are obtained less than -30 V bias condition. The result is one of the best reported performances of pentacene TFTs with hybrid insulator including cross-linked PVA layer as a gate insulator at relatively low voltage operation.

Triple Layer Passivation for Organic Thin-Film Transistors

  • Ryoo, Ki-Hyun;Lee, Cheon-An;Jin, Sung-Hun;Jung, Keum-Dong;Park, Chang-Bum;Lee, Jong-Duk;Shin, Hyung-Cheol;Park, Byung-Gook
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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    • pp.1310-1312
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    • 2005
  • Passivation of organic thin-film transistors (OTFTs) using organic and metal thin-film was presented. Parylene-C and titanium were used as an organic and metal layer, respectively. With the proposed passivation method the degradation of electric parameters of OTFTs was relieved compared with non-passivated devices. Several electric parameters such as on/off current, field-effect mobility, and threshold voltage were shown.

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