• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2002년도 추계학술대회 발표 논문집
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• pp.72-74
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• 2002

A submicron contact scheme using $WN_x$ diffusion barrier has been suggested for multilevel interconnect structure. The contact resistance of $0.4\times0.48\mu\textrm{m}^2$ size Al/WN/Ti/$n^+$-Si is 120-140 $\Omega$ and the leakage current density is below than $10^{-16}$$-10^{-15}A/\mu\textrm{m}^2$. The effect of F atoms on the submicron contact has been investigated with the nuclear resonance analysis method.

• 한국전기전자재료학회논문지
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• 제13권3호
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• pp.200-205
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• 2000

This paper describes the structure modeling and operation characteristics of MFMIS(metal-ferroelectric-metal-insulator-semiconductor) device using the Tsuprem4 which is a semiconductor device tool by Avanti. MFMIS device is being studied for nonvolatile memory application at various semiconductor laboratory but it is difficult to fabricate and analyze MFMIS devices using the semiconductor simulation tool: Tsuprem4, medici and etc. So the new library and new materials parameters for adjusting ferroelectric material and platinum electrodes in the tools are studied. In this paper structural model and operation characteristics of MFMIS devices are measured, which can be easily adopted to analysis of MFMIS device for nonvolatile memory device application.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.38-47
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• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.1418-1419
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• 2011

차세대 전력 반도체인 고전압 GaN 쇼트키 장벽 다이오드의 역방향 특성을 개선하기 위해서 열 산화공정이 제안되었다. AlGaN/GaN 에피탁시 위에 쇼트키 장벽 다이오드 구조가 제작되었으며, 쇼트키 컨택은 증착 후 $450^{\circ}C$에서 산화되었다. 열 산화공정이 메사 측벽의 AlGaN 및 GaN 표면에 $AlO_x$ 및 $GaO_x$를 형성하여 표면으로 흐르는 누설전류를 억제한다. 표면 및 GaN 버퍼를 통한 누설전류는 열 산화 공정 이후 100 ${\mu}m$-너비당 51.3 nA에서 24.9 pA로 1/2000 배 수준으로 감소하였다. 표면 산화물 형성으로 인하여 생성된 Ga-vacancy와 Al-vacancy는 acceptor로 동작하여 surface band bending을 증가시켜 쇼트키 장벽 높이를 증가시킨다. 애노드-캐소드 간격이 5 ${\mu}m$인 제작된 소자는 0.99 eV의 높은 쇼트키 장벽 높이를 획득하여, -100 V에서 0.002 A/$cm^2$의 낮은 누설전류를 확보하였다. 애노드-캐소드 간격이 5에서 10, 20, 50 ${\mu}m$로 증가되면 소자의 항복전압은 348 V에서 396, 606, 941 V로 증가되었다. 열 산화공정은 전력용 GaN 전자소자의 누설전류감소와 항복전압 증가를 위한 후처리 공정으로 적합하다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.797-801
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• 2014

This research presented the concept of employing the punch-through diode triggered SCRs (PTTSCR) for low voltage ESD applications such as transient voltage suppression (TVS) devices. In order to demonstrate the better electrical properties, various traditional ESD protection devices, including a silicon controlled rectifier (SCR) and Zener diode, were simulated and analyzed by using the TCAD simulation software. The simulation result demonstrates that the novel PTTSCR device has better performance in responding to ESD properties, including DC dynamic resistance and capacitance, compared to SCR and Zener diode. Furthermore, the proposed PTTSCR device has a low reverse leakage current that is below $10^{-12}$ A, a low capacitance of $0.07fF/mm^2$, and low triggering voltage of 8.5 V at $5.6{\times}10^{-5}$ A. The typical properties couple with the holding voltage of 4.8 V, while the novel PTTSCR device is compatible for protecting the low voltage, high speed ESD protection applications. It proves to be good candidates as ultra-low capacitance TVS devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.280-283
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• 2004

This paper discribes the design concept, fabrication process and measuring result of 2.5kV Gate Commutated Thyristor devices. Integrated gate commutated thyristors(IGCTs) is the new power semiconductor device used for high power inverter, converter, static var compensator(SVC) etc. Most of the ordinary GTOs(gate turn-off thyristors) are designed as non-punch-through(NPT) concept; i.e. the electric field is reduced to zero within the N-base region. In this paper, we propose transparent anode structure for fast turn-off characteristics. And also, to reach high breakdown voltage, we used 2-stage bevel structure. Bevel angle is very important for high power devices, such as thyristor structure devices. For cathode topology, we designed 430 cathode fingers. Each finger has designed $200{\mu}m$ width and $2600{\mu}m$ length. The breakdown voltage between cathode and anode contact of this fabricated GCT device is 2,715V.

• Journal of Mechanical Science and Technology
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• 제17권12호
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• pp.2099-2106
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• 2003

In this paper, a novel fast response NDIR analyzer (FRNDIR), which uses an electrically pulsed semiconductor emitter and dual type PbSe detector for the PPM-level detection of carbon dioxide (CO$_2$) at a wavelength of 4.28 $\mu\textrm{m}$, is described. Modulation of conventional NDIR energy typically occurs at 1 to 20 Hz. To achieve real time high-speed measurement, the new analyzer employs a semiconductor light emitter that can be modulated by electrical chopping. Updated measurements are obtained every one millisecond. The detector has two independent lead selenide (PbSe) with IR band pass filters. Both the emitter accuracy and the detector sensitivity are increased by thermoelectric cooling of up to -20 degrees C in all semiconductor devices. Here we report the use of semiconductor devices to achieve improved performance such that these devices have potential application to CO$_2$ gas measurement and, in particular, the measurement of fast response CO$_2$ concentration at millisecond level.

• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2009년도 춘계학술발표논문집
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• pp.311-313
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• 2009

최근 심각한 환경오염 문제와 화석 에너지 고갈로 차세대 청정에너지 개발에 대한 중요성이 증대되고 있다. 그 중에서 태양전지는 공해가 적고, 자원이 무한적이며 반영구적인 수명을 가지고 있어 미래 에너지 문제를 해결할 수 있는 에너지원으로 기대되고 있다. 태양전지 기술 개발 방향은 발전 단가를 낮추는 태양전지 변환 효율 개선 연구위주로 연구가 진행되어 왔다. 태양전지의 변환 효율은 새로운 물질의 개발과 개선된 등으로 통하여 연구가 진행되어 왔다. 하지만, 태양전지를 개발하는데 있어서 많은 비용을 차지하는 것은 제조공정의 단순화가 우선일 것이다. 본 연구에서는 태양전지 제작하는 공정을 단순화 하고 그 공정 중에 생성되는 박막의 표면 분석에 대한 연구를 진행하였다. 낮추기 위하여 저가로 대량 생산이 가능하도록 다양한 물질과 공정이 개발되었지만, 변환 효율이 낮아 상용화에 큰 걸림돌이 되고 있다. 또한 변환 효율 향상을 위한 연구는 과거에는 변환 효율이 높은 물질을 찾기 위해 다양한 시도가 이루어졌으며, 현재는 물질 합성과 적층 구조 등을 이용하여 광흡수 대역을 넓혀 변환 효율을 높이는데 주력하고 있다.

• 한국전기전자재료학회논문지
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• 제37권3호
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• pp.241-252
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• 2024

With the recent development of emerging technologies, information acquisition and delivery between users has been actively conducted, and inorganic thin film transfer technology that effectively transfers various materials and devices is being studied to develop flexible electronic devices accordingly. This is aimed at innovative structural changes and functional improvement of electronic devices in the era of the Internet of Things (IoT). In particular, advanced technologies such as microLEDs are used to realize high-resolution flexible displays, and the possibility of heterogeneous integrated technologies can be presented by precisely transferring materials to substrates through various transfer process. This paper introduced physical, chemical, and self-assembly transfer methods based on inorganic thin film materials to implement heterogeneous integrated flexible semiconductor systems and introduces the results of application studies of semiconductor devices obtained through different transfer technologies. These studies are expected to bring about innovative changes in the field of smart devices, medical technology, and user interfaces in the future.

• 조명전기설비학회논문지
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• 제18권1호
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• pp.105-114
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• 2004

본 논문에서 반도체 소자에 대한 DC 파라미터 검사를 위한 회로를 설계하였다. DC 파라미터 검사기는 반도체 소자의 DC 특성을 검사하는 시스템 이다. 본 논문에서 설계한 회로에서는 파라미터를 검사하기 위해 전압(전류)인가 전류(전압)측정 방법을 사용하도록 회로를 설계하였다. 설계한 회로를 OR-CAD를 사용하여 실험하였으며, 설계된 회로의 실험결과를 통해 좋은 성능을 가짐을 알 수 있었다.