• 반도체디스플레이기술학회지
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• 제12권2호
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• pp.39-43
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• 2013

The semiconductor equipments generate necessary data through communication networks for the effective manufacturing processes and automation of semiconductor equipments. For transferring data between semiconductor equipments and sending data to monitor equipments, several standards for communication protocols have been proposed. Communication networks in semiconductor manufacturing systems will transmit a lot of data traffic, which can be vulnerable in data delay and network failure. Therefore, it is required that data traffic need to be distributed. To accomplish this objective, we recommend the use of a redundant and valuable communication path which is constructed by a wireless sensor network. In this paper, the directed diffusion method for wireless sensor networking is suggested for networking semiconductor equipments. It is shown that how the directed diffusion is employed to connect semiconductor equipments. Also, we show how to implement the SECS of semiconductor equipments communication protocols based on the directed diffusion.

• 대한산업공학회지
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• 제36권3호
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• pp.154-163
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• 2010

Process monitoring of output variables affecting final performance have been mainly executed in semiconductor manufacturing process. However, even earlier detection of causes of output variation cannot completely prevent yield loss because a number of wafers after detecting them must be re-processed or cast away. Semiconductor manufacturers have put more attention toward monitoring process inputs to prevent yield loss by early detecting change-point of the process. In the paper, we propose the method to efficiently monitor functional input variables in multi-phase semiconductor manufacturing process. Measured input variables in the multi-phase process tend to be of functional structured form. After data pre-processing for these functional input data, change-point analysis is practiced to the pre-processed data set. If process variation occurs, key variables affecting process variation are selected using contribution plot for monitoring efficiency. To evaluate the propriety of proposed monitoring method, we used real data set in semiconductor manufacturing process. The experiment shows that the proposed method has better performance than previous output monitoring method in terms of fault detection and process monitoring.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.108-112
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• 2023

Precision manufacturing technology is rapidly developing due to the extreme miniaturization of semiconductor processes to comply with Moore's Law. Accurate and precise alignment, which is one of the key elements of the semiconductor pre-process and post-process, is very important in the semiconductor process. The center detection of wafer align marks plays a key role in improving yield by reducing defects and research on accurate detection methods for this is necessary. Methods for accurate alignment using traditional image sensors can cause problems due to changes in image brightness and noise. To solve this problem, engineers must go directly into the line and perform maintenance work. This paper emphasizes that the development of AI technology can provide innovative solutions in the semiconductor process as high-resolution image and image processing technology also develops. This study proposes a new wafer center detection method through variable thresholding. And this study introduces a method for detecting the center that is less sensitive to the brightness of LEDs by utilizing a high-performance object detection model such as YOLOv8 without relying on existing algorithms. Through this, we aim to enable precise wafer focus detection using artificial intelligence.

• 제어로봇시스템학회논문지
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• 제5권6호
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• pp.724-733
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• 1999

An effective method of system modeling and dynamic scheduling for the back-end line of semiconductor manufacturing is proposed. The virtual factory, describing semiconductor manufacturing line, is designed in detail, and then a Petri net model simulator is developed for operation and control of the modular cells of the virtual factory. The petri net model is a colored timed Petri nets (CTPNs). The simulator will be utilized to analyze and evaluate various dynamic status and operatons of manufacturing environments. The dynamic schedulaer has a hierarchical structure with the higher for planning level and the lower for dynamic scheduling level. The genetic algorithm is applied to extract optimal conditions of the scheduling algorithm. The proposed dynamic scheduling is able to realize the semiconductor manufacturing environments for the diversity of products, the variety of orders by many customers, the flexibility of order change by changing market conditions, the complexity of manufacturing processes, and the uncertainty of manufacturing resources. The proposed method of dynamic scheduling is more effective and useful in dealing with such recent pressing requirements including on-time delivery, quick response, and flexibility.

• 대한산업공학회지
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• 제41권6호
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• pp.579-587
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• 2015

Semiconductor manufacturing industry is a high density integration industry because it generates a vest number of data that takes about 300~400 processes that is supervised by numerous production parameters. It is asked of engineers to understand the correlation between different stages of the manufacturing process which is crucial in reducing production costs. With complex manufacturing processes, and defect processing time being the main cause. In the past, it was possible to grasp the corelation among manufacturing process stages through the engineer's domain knowledge. However, It is impossible to understand the corelation among manufacturing processes nowadays due to high density integration in current semiconductor manufacturing. in this paper we propose a canonical correlation analysis (CCA) using both wafer test voltage variables and fail bit counts variables. using the method we suggested, we can increase the semiconductor yield which is the result of the package test.

• 산업공학
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• 제13권3호
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• pp.348-357
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• 2000

SCM(Supply Chain Management) is a new approach to satisfy customers via an integrated management for the whole business processes of the manufacturing from the raw material procurement to the product or service delivery to customers. Typically the semiconductor industry is the one whose supply chain network is distributed all over the world, and its manufacturing process has the particular characteristics which has to be considered in the modeling of supply chain. In this paper we suggest the push and pull type supply chain models based on the manufacturing characteristics and their mathematical formulation for the semiconductor industry. Push supply chain model pursuits the high throughput and the balance of the WIP flow, and pull supply chain model does to minimize the total cost of order-based manufacturing, distribution and transportation process in order to meet customer's request appropriately.

• 분석과학
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• 제5권4호
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• pp.455-464
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• 1992

본 논문에서는 FT-IR 분광분석법을 이용하여 여러 가지 반응조건에서 기체상 silylation 반응에 의해 생성된 silylated layer의 depth를 비파괴적으로 정량하는 방법을 제안하였다. Silylated layer의 depth는 FT-IR 스펙트럼의 특성 봉우리들(Si-O-ph, Si-C, Si-H)의 흡광도를 바탕 스펙트럼 공제법으로 측정하여 SEM의 두께 측정치와 비교하여 정량하였다. FT-IR 분광분석법을 이용한 Silylated layer의 depth 분석은 비파괴적이고 정량적인 방법으로, 이 방법은 silylation process window를 설정하는 데 적합하다는 것을 알았다.

• 분석과학
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• 제5권4호
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• pp.359-366
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• 1992

본 논문은 마이크로 Raman 분광분석법을 이용하여 국부적 열산화 후 실리콘 표면에 유입되는 스트레스를 평가한 것이다. 국부적 열산화 후 실리콘 표면에 유입되는 스트레스는 실리콘 산화막과 active 영역의 경계 부분에서 최대치를 나타내었다. Active 영역의 크기가 작아질수록 스트레스량은 증가하며, 이는 스트레스가 active 영역의 크기에 의존함을 보여 주는 것이다. 또한, active 영역이 $0.45{\mu}m$인 세 가지 소자 분리 공정, A, B, moB를 평가한 결과 moB 공정의 스트레스 값이 가장 작았으며, 새부리 효과도 가장 작았다.

• 반도체디스플레이기술학회지
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• 제22권1호
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• pp.124-128
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• 2023

반도체 양산을 진행하며 얻어지는 여러 공정 데이터들로 사용 전압을 예측하여 에너지 효율적인 제품을 위한 목적으로 연구를 시작했다. 각각의 feature들 단독으로 전압을 예측하기 어려웠던 문제를 머신 러닝을 통해, 특히 Ensemble model을 이용함으로써 단일 모델보다 정확한 예측을 할 수 있었다. 더욱 중요한 시사점으로는 feature importance 분석을 통해 모델 예측에 영향이 큰 feature와 작은 feature에 대한 분석이다. 영향도가 높은 feature를 통해 비슷한 계열의 측정값을 늘리고, 낮은 feature 들의 문제점을 개선함으로써 차세대 제품에서 더욱 정확도 높은 모델을 위한 발판을 마련할 수 있었다.

• 한국시뮬레이션학회논문지
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• 제18권4호
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• pp.219-225
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• 2009

본 연구는 복잡하고 다양한 반도체 웨이퍼 가공(FAB) 공정의 전체적인 흐름을 컴퓨터 모델로 구축하고 이를 Device 단면도를 나타내는 프리젠테이션 툴과 연동시키는 교육 모델의 개발을 목적으로 하였다. 급변하는 세계 반도체 시장에서 국내 반도체 업체는 지속적인 기술 개발과 더불어 효율적인 생산관리에 대응할 수 있도록 하여 국제 경쟁력을 키워야 할 것이다. 따라서 본 연구에서 다루어진 공정의 흐름과 각 단위공정의 특성을 바탕으로 설립된 모델은 서울대학교 반도체 공동 연구소를 대상으로 구현되었으나 앞으로 생산 관리를 담당할 국내 반도체 업체들의 신입사원과 현장기술자의 질적 향상을 위한 시청각 교육용 자료로의 활용 시 상당한 효과를 거둘 것이라 예상된다. 이는 생산업체에 국한되어지는 것만은 아니며 반도체 공정에 관련된 대학 학과목에서도 활용되어지리라 생각된다. 또한 확장성과변화에 유연한 모델을 개발함으로써 반도체 생산 업체들은 구성된 표준 모델을 이용하여 각 회사의 실정에 맞추어 자사에 대한 시뮬레이션을 손쉽게 수행함으로써 많은 교육 효과와 이에 따른 원가 절감의 효과까지 거둘 수 있을 것이다.