• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.70-79
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• 2016

This paper proposes a low-power range-scaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a sampling-time mismatch as observed in the conventional SHA-free architecture. A range-scaling technique processes a wide input range of 3.0VP-P without thick-gate-oxide transistors under a 1.8 V supply voltage. The first- and second-stage MDACs share a single amplifier to reduce power consumption and chip area. Moreover, two separate reference voltage drivers for the first-stage SAR ADC and the remaining pipeline stages reduce a reference voltage disturbance caused by the high-speed switching noise from the SAR ADC. The measured DNL and INL of the prototype ADC in a $0.18{\mu}m$ CMOS are within 0.88 LSB and 3.28 LSB, respectively. The ADC shows a maximum SNDR of 65.4 dB and SFDR of 78.9 dB at 30 MS/s, respectively. The ADC with an active die area of $1.43mm^2$ consumes 20.5 mW at a 1.8 V supply voltage and 30 MS/s, which corresponds to a figure-of-merit (FOM) of 0.45 pJ/conversion-step.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.47-52
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• 2013

Gold wire has long been used as a proven method of connecting a silicon die to a substrate in wide variety of package types, delivering high yield and productivity. However, with the high price of gold, the semiconductor packaging industry has been implementing an alternate wire material. These materials may include silver (Ag) or copper (Cu) alloys as an alternative to save material cost and maintain electrical performance. This paper will analyze and compare the electrical characteristics of several wire types. For the study, typical 0.6 mil, 0.8 mil and 1.0 mil diameter wires were selected from various alloy types (2N gold, Palladium (Pd) coated/doped copper, 88% and 96% silver) as well as respective pure metallic wires for comparison. Each wire model was validated by comparing it to electromagnetic simulation results and measurement data. Measurements from the implemented test boards were done using a vector network analyzer (VNA) and probe station setup. The test board layout consisted of three parts: 1. Analysis of the diameter, length and material characteristic of each wire; 2. Comparison between a microstrip line and the wire to microstrip line transition; and 3. Analysis of the wire's cross-talk. These areas will be discussed in detail along with all the extracted results from each type the wire.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.131-135
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• 2005

The effect of different surface passivation films on blue or green (465-505 nm) InGaN/GaN multi-quantum well light-emitting diodes (LEDs) die were examined. $SiO_2$ or $SiN_x$ deposited by plasma enhanced chemical vapor deposition, or $Sc_2O_3$ or MgO deposited by rf plasma enhanced molecular beam epitaxy all show excellent passivation qualities. The forward current-voltage (I-V) characteristics were all independent of the passivation film used, even though the MBE-deposited films have lower interface state densities ($3-5{\times}10^{12}\;eV^{-1}\;cm^{-2}$) compared to the PECVD films (${\sim}10^{12}\;eV^{-1}\;cm^{-2}$), The reverse I-V characteristics showed more variation, hut there was no systematic difference for any of the passivation films, The results suggest that simple PECVD processes are effective for providing robust surface protection for InGaN/GaN LEDs.

• Journal of the Korean Society for Nondestructive Testing
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• v.19 no.5
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• pp.369-377
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• 1999

Recently, it is gradually raised necessity that thickness of thin film is measured accuracy and managed in industrial circles and medical world. Ultrasonic signal processing method is likely to become a very powerful method for NDE method of detection of microdefects and thickness measurement of thin film below the limit of ultrasonic distance resolution in the opaque materials, provides useful information that cannot be obtained by a conventional measuring system. In the present research. considering a thin film below the limit of ultrasonic distance resolution sandwiched between three substances as acoustical analysis model, demonstrated the usefulness of ultrasonic signal processing technique using information of ultrasonic frequency for NDE of measurements of thin film thickness. Accordingly, for the detection of delamination between the junction condition of boundary microdefect of thin film sandwiched between three substances the results from digital image processing.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.777-788
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• 2014

This paper presents a wide output range, high power efficiency reconfigurable charge pump for driving touch panels with the high resistances. The charge pump is composed of 4-stages and its configuration automatically changes based on the required output voltage level. In order to keep the power efficiency over the wide output voltage range, internal blocks are automatically activated or deactivated by the clock driver in the reconfigurable charge pump minimizing the switching power loss due to the On and Off operations of MOSFET. In addition, the leakage current paths in each mode are blocked to compensate for the variation of power efficiency with respect to the wide output voltage range. This chip is fabricated using $0.18{\mu}m$ BCD process with high power MOSFET options, and the die area is $1870{\mu}m{\times}1430{\mu}m$. The power consumption of the charge pump itself is 79.13 mW when the output power is 415.45 mW at the high voltage mode, while it is 20.097 mW when the output power is 89.903 mW at the low voltage mode. The measured maximum power efficiency is 84.01 %, when the output voltage is from 7.43 V to 12.23 V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.95-103
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• 2011

This paper proposes a 6b 1.2 GS/s 47.8 mW 0.17 $mm^2$ 65 nm CMOS ADC for high-rate wireless personal area network systems. The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 $V_{p-p}$ at a 1.2 V supply voltage to minimize power consumption and high comparator offset effects in a nanometer CMOS technology. The track-and-hold circuits without source followers, the differential difference amplifiers with active loads in pre-amps, and the output averaging layout scheme properly handle a wide-range input signal with low distortion. The interpolation scheme halves the required number of pre-amps while three-stage cascaded latches implement a skew-free GS/s operation. The two-step bubble correction logic removes a maximum of three consecutive bubble code errors. The prototype ADC in a 65 nm CMOS demonstrates a measured DNL and INL within 0.77 LSB and 0.98 LSB, respectively. The ADC shows a maximum SNDR of 33.2 dB and a maximum SFDR of 44.7 dB at 1.2 GS/s. The ADC with an active die area of 0.17 $mm^2$ consumes 47.8 mW at 1.2 V and 1.2 GS/s.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.3
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• pp.563-569
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• 2007

As the mobile communication and the semiconductor technology is improved continuously, mobile contents such as the multimedia service and the 2D/3D graphics which require high level graphics are serviced recently. Mobile chips should consume small die area and low power. In this paper, we design a truncated floating-point multiplier that is useful for the 2D/3D vector graphics in mobile devices. The truncated multiplier is based on the radix-4 Booth's encoding algorithm and a truncation algorithm is used to achieve small area and low power. The average percent error of the multiplier is as small as 0.00003% and neglectable for mobile applications. The synthesis result using 0.35um CMOS cell library shows that the number of gates for the truncated multiplier is only 33.8 percent of the conventional radix-4 Booth's multiplier.

• Journal of IKEEE
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• v.26 no.4
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• pp.537-544
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• 2022

This paper analyzes the occurrence and cause of bond wires fusing used in the manufacture of pulsed high power amplifiers. Recently GaN HEMT has been spotlight in the fields of electronic warfare, radar, base station and satellite communication. In order to produce the maximum output power, which is the main performance of the high-power amplifier, optimal impedance matching is required. And the material, diameter and number of bond wires must be determined in consideration of not only the rated current but also the heat generated by the transient current. In particular, it was confirmed that compound semiconductor with a wide energy band gap such as GaN trigger fusing of the bond wire due to an increase in thermal resistance when the design efficiency is low or the heat dissipation is insufficient. This data has been simulated for exothermic conditions, and it is expected to be used as a reference for applications using GaN devices as verified through IR microscope.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.4
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• pp.50-60
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• 2023

Ball Grid Array (BGA) is a widely used package type due to its high pin density and good heat dissipation. In BGA, solder balls play an important role in electrically connecting the package to the PCB. Therefore, understanding the inelastic deformation of solder balls under various mechanical loads is essential for the robust design of semiconductor packages. In this study, the geometrical effect on the inelastic deformation and fracture of solder balls were analyzed by finite element analysis. The results showed that fracture occurred in both tilted and hourglass shapes under shear loading, and no fracture occurred in all cases under compressive loading. However, when bending was applied, only the tilted shape failed. When shear and bending loads were combined with compression, the stress triaxiality was maintained at a value less than zero and failure was suppressed. Furthermore, a comparison using the Lagrangian-Green strain tensor of the critical element showed that even under the same loading conditions, there was a significant difference in deformation depending on the shape of the solder ball.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.49-60
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• 2010

Semiconductor packages are increasingly moving toward miniaturization, lighter and high performance. Futhermore, packages become thinner. Thin packages will generate serious reliability problems such as warpage, crack and other failures. Reliability problems are mainly caused by the CTE mismatch of various package materials. Therefore, proper selection of the package materials and geometrical optimization is very important for controlling the warpage and the stress of the package. In this study, we investigated the characteristics of the warpage and the stress of several packages currently used in mobile devices such as CABGA, fcSCP, SCSP, and MCP. Warpage and stress distribution are analyzed by the finite element simulation. Key material properties which affect the warpage of package are investigated such as the elastic moduli, CTEs of EMC molding and the substrate. Geometrical effects are also investigated including the thickness or size of EMC molding, silicon die and substrate. The simulation results indicate that the most influential factors on warpage are EMC molding thickness, CTE of EMC, elastic modulus of the substrate. Simulation results show that warpage is the largest for SCSP. In order to reduce the warpage, DOE optimization is performed, and the optimization results show that warpage of SCSP becomes $10{\mu}m$.