• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1892-1897
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• 2012

In this paper, efficient CNU(Check Node Update) algorithms are analyzed for high speed LDPC decoding in DVB-S2 standard. In aspect to CNU methods, there are some kinds of CNU methods. Among of them, MP (Min Product) method is quite often used in LDPC decoding. However MP needs LUT (Look Up Table) that is critical path in LDPC decoding speed. A new SC-NMS (Self-Corrected Normalized Min-Sum) method is proposed in the paper. NMS needs only normalized scaling factor instead of LUT and compensates the overestimation of MP approximation. In addition, SC method is proposed. It gives a faster convergence toward a decoded codeword. If a message change its sign between two iterations, it is not reliable and to avoid to propagate noisy information, its module is set to 0. The performance of SC-NMS has a little degrade compare to MP by 0.1 dB, however considering computational complexity and decoding speed, SC-NMS algorithm is optimal method for CNU algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.2
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• pp.140-145
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• 2013

This paper proposes the high speed LDPC decoder structure base on the DVB-S2. Firstly, We study the solution to avoid the memory conflict. For the high speed decoding process the decoder adapts the HSS(Horizontal Shuffle Scheduling) scheme. Secondly, for the high speed decoding algorithm normalized Min-Sum algorithm is adapted instead of Sum-Product algorithm. And the self corrected is a variant of the LDPC decoding that sets the reliability of a Mc${\rightarrow}$v message to 0 if there is an inconsistency between the signs of the current incoming messages Mv'${\rightarrow}$c and the sign of the previous incoming messages Moldv'${\rightarrow}$c This self-corrected algorithm avoids the propagation on unreliable information in the Tanner graph and thus, helps the convergence of the decoder.Start after striking space key 2 times. Lastly, and this paper propose the optimal hardware architecture supporting the high speed throughput.