• JSTS:Journal of Semiconductor Technology and Science
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• 제3권1호
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• pp.1-12
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• 2003

This paper describes a study on the abnormal behavior of the electrical characteristics of the (n)GaAs/Ti/Pt/Au Schottky contacts prepared by the two techniques of electron beam deposition and rf sputtering and after an annealing treatment. The samples were characterized by I-V and C-V measurements carried out over the temperature range of 150 - 350 K both in the as prepared state and after a 300 C, 30 min. anneal step. The variation of ideality factor with forward bias, the variation of ideality factor and barrier height with temperature and the difference between the capacitance barrier and current barrier show the presence of a thin interfacial oxide layer along with barrier height inhomogenieties at the metal/semiconductor interface. This barrier height inhomogeneity model also explains the lower barrier height for the sputtered samples to be due to the presence of low barrier height patches produced because of high plasma energy. After the annealing step the contacts prepared by electron beam have the highest typical current barrier height of 0.85 eV and capacitance barrier height of 0.86 eV whereas those prepared by sputtering (at the highest power studied) have the lowest typical current barrier height of 0.67 eV and capacitance barrier height of 0.78 eV.

• 대한전자공학회논문지
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• 제20권3호
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• pp.33-39
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• 1983

종래의 쇼트키 다이오드들이 가지는 금속중첩 및 P보호환 구조와 비교하여 금속-반도체 접합면 가장자리에 얇은 계단형 산화막(약1000Å) 구조를 갖는 새로운 소자들을 설계 제작하였다. 별은 계단형 산화막의 형성은 T.C.E. 산화공정으로 처리하였으며 이러한 새로운 소자들의 항복현상을 비교 검토하기 위하여 이들과 함께 동일한 소자 크기를 갖는 종래의 금속 중첩 쇼트키 다이오드와 P보호환 쇼트키 다이오드를 같은 폐이퍼상에 집적시켰고 항복전압에 대한 측정을 통해 고찰해 본 결과 금속-반도체 접합면 가장자리에 얇은 계단형 산화막 구조를 갖는 소자들은 종래의 쇼트키 다이오드들에 비해 항복현상에 있어서 월등한 개선을 보여 주는 것으로 나타났다.

• Transactions on Electrical and Electronic Materials
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• 제16권3호
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• pp.151-155
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• 2015

We fabricated the Cu Schottky contact on an n-type Ge wafer and investigated the forward bias current-voltage (I-V) characteristics in the temperature range of 100~300 K. The zero bias barrier height and ideality factor were determined based on the thermionic emission (TE) model. The barrier height increased and the ideality factor decreased with increasing temperature. Such temperature dependence of the barrier height and the ideality factor was associated with spatially inhomogeneous Schottky barriers. A notable deviation from the theoretical Richardson constant (140.0 Acm^-2K^-2 for n-Ge) on the conventional Richardson plot was alleviated by using the modified Richardson plot, which yielded the Richardson constant of 392.5 Acm^-2K^-2. Finally, we applied the theory of space-charge-limitedcurrent (SCLC) transport to the high forward bias region to find the density of localized defect states (N_t), which was determined to be 1.46 × 10¹² eV^-1cm^-3.

• E2M - 전기 전자와 첨단 소재
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• 제9권10호
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• pp.1013-1018
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• 1996

The annealing effects of Au/Te/Au/n-GaAs structure was investigated by using x-ray diffraction, scanning electron microscope, the specific contact resistance and I-V measurement. Increasing the annealing temperature, the intensity of Au-Ga peak by X-ray diffraction was increased. The Ga$\_$2/Te$\_$3/peak got evident for the samples annealed at 400.deg. C and GaAs peak by recrystallization appeared for the samples annealed at 500.deg. C. The variation from the schottky to low resistance contact was confirmed by I-V curve. The lowest value of the specific contact resistance of the samples annealed at 500.deg. C was 3.8*10$\^$-5/.ohm.-cm$\^$2/ but the value increased above 600.deg. C.

• 한국산학기술학회논문지
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• 제20권7호
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• pp.16-19
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• 2019

박막이 얇아질수록 전기적인 특성이 좋아지려면 비정질구조가 유리하다. 비정질구조는 케리어가 공핍되는 특징을 이용하여 전도성을 높이는데 효과가 있을 수 있다. 이러한 특성을 확인하는 방법으로 전위장벽이 형성되는 쇼키접합에 대한 연구가 필요하다. 비정질구조와 쇼키접합에 대하여 조사하기 위하여 $SiO_2/SnO_2$ 박막을 준비하였으며, $SiO_2$ 박막은 Ar=20 sccm 만들고 $SnO_2$ 박막은 아르곤과 산소의 유량을 각각 20 sccm으로 혼합가스를 사용하였으며, 마그네트론 스퍼터링 방법으로 $SnO_2$의을 증착하고 $100^{\circ}C$와 $150^{\circ}C$에서 열처리를 하였다. 비정질구조가 만들어지는 조건을 알아보기 위하여 XRD 패턴을 조사하고 C-V, I-V 측정을 실시하여 Al 전극을 만들고 전기적인 분석을 실시하였다. 공핍층은 열처리과정을 통하여 전자와 홀의 재결합으로 형성되는데 $SiO_2/SnO_2$ 박막은 $100^{\circ}C$에서 열처리를 한 경우 공핍층이 잘 형성이 되었으며, 미시영역에서는 전기적으로 전류가 크게 작용하는 것을 확인하였다. $100^{\circ}C$에서 열처리를 한 비정질의 $SiO_2/SnO_2$ 박막은 XRD 패턴에서 $33^{\circ}$에서는 픽이 나타나지 않았으며, $44^{\circ}$에서는 픽이 생겼다. 쇼키접합에 의해서 거시적(-30V<전압<30V)으로는 절연체 특성이 보였으나 미시적(-5V<전압<5V)으로는 전도성이 나타났다. 케리어가 부족한 공핍층에서의 전도는 확산전류에 의하여 전도가 이루어진다. 미소영역에서 동작하는 소자인 경우에는 공핍효과에 의한 쇼키접합이 전류의 발생과 전도에 유리하다는 것을 확인하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.318.2-318.2
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• 2014

The high contact resistance is still one of the major issues to be resolved in CdS/CdTe thin film solar cells. CdTe/Metal Schottky contact induced a high contact resistance in CdS/CdTe solar cells. It has been reported that the work function of CdTe thin film is more than 5.7 eV. There has not been a suitable back contact metal, because CdTe thin film has a high work function. In a few decades, some buffer layer was reported to improve a back contact problem. Buffer layers which are Te, $Sb_2Te_3$, $Cu_2Te$, ZnTe:Cu and so on was inserted between CdTe and metal electrode. A formed buffer layers made a tunnel junction. Hole carriers which was excited in CdTe film by light absorption was transported from CdTe to back metal electrode. In this report, we reported the variation of solar cell performance with different buffer layer at the back contact of CdTe thin film solar cell.

• 한국재료학회지
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• 제13권1호
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• pp.11-17
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• 2003

DC characteristics of recessed gate 4H-SiC MESFET were investigated using the device/circuit simulation tool, PISCES. Results of theoretical calculation were compared with the experimental data for the extraction of modeling parameters which were implemented for the prediction of DC and gate leakage characteristics at high temperatures. The current-voltage analysis using a fixed mobility model revealed that the short channel effect is influenced by the defects in SiC. The incomplete ionization models are found out significant physical models for an accurate prediction of SiC device performance. Gate leakage is shown to increase with the device operation temperatures and to decrease with the Schottky barrier height of gate metal.

• Transactions on Electrical and Electronic Materials
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• 제17권5호
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• pp.293-296
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• 2016

Using capacitance-voltage (C-V) and conductance-voltage (G/ω-V) measurements, the electrical properties of Cu/n-InP Schottky diodes were investigated. The values of C and G/ω were found to decrease with increasing frequency. The presence of interface states might cause excess capacitance, leading to frequency dispersion. The negative capacitance was observed under a forward bias voltage, which may be due to contact injection, interface states or minority-carrier injection. The barrier heights from C-V measurements were found to depend on the frequency. In particular, the barrier height at 200 kHz was found to be 0.65 eV, which was similar to the flat band barrier height of 0.66 eV.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.238-242
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• 2001

In this paper, the current-voltage characteristics of a 4H-SiC MESFET is simulated by using the Atlas Simulation tool. we are able to use the simulator to extract more information about the new material 4H-SiC, including the mobility, velocity-field Curve and the Schottky barrier height. We have enabled and used the new simulator to investigate breakdown Voltage and thus predict operation limitiations of 4H-SiC device. Modeling results indicate that the Breakdown Voltage is 197 V and Current is 100 mA

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.238-242
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• 2001

In this paper, the current-voltage characteristics of a 4H-SiC MESFET is simulated by using the Atlas Simulation tool. we are able to use the simulator to extract more information about the new material 4H-SiC, including the mobility, velocity-field Curve and the Schottky barrier height. We have enabled and used the new simulator to investigate breakdown Voltage and thus predict operation limitations of 4H-SiC device. Modeling results indicate that the Breakdown Voltage is 197 V and Current is 100 mA