• Title/Summary/Keyword: Scheduling optimization

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Design of Experiment and Analysis Method for the Integrated Logistics System Using Orthogonal Array (직교배열을 이용한 통합물류시스템의 실험 설계 및 분석방법)

  • Park, Youl-Kee;Um, In-Sup;Lee, Hong-Chul
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.12 no.12
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    • pp.5622-5632
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    • 2011
  • This paper presents the simulation design and analysis of Integrated Logistics System(ILS) which is operated by using the AGV(Automated Guided Vehicle). To maximize the operation performances of ILS with AGV, many parameters should be considered such as the number, velocity, and dispatching rule of AGV, part types, scheduling, and buffer sizes. We established the design of experiment in a way of Orthogonal Array in order to consider (1)maximizing the throughput; (2)maximizing the vehicle utilization; (3)minimizing the congestion; and (4)maximizing the Automated Storage and Retrieval System(AS/RS) utilization among various critical factors. Furthermore, we performed the optimization by using the simulation-based analysis and Evolution Strategy(ES). As a result, Orthogonal Array which is conducted far fewer than ES significantly saved not only the time but the same outcome when compared after validation test on the result from the two methods. Therefore, this approach ensures the confidence and provides better process for quick analysis by specifying exact experiment outcome even though it provides small number of experiment.

Design of an Efficient Control System for Harbor Terminal based on the Commercial Network (상용망 기반의 항만터미널 효율적인 관제시스템 설계)

  • Kim, Yong-Ho;Ju, YoungKwan;Mun, Hyung-Jin
    • Journal of Industrial Convergence
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    • v.16 no.1
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    • pp.21-26
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    • 2018
  • The Seaborne Trade Volume accounts for 97% of the total. This means that the port operation management system can improve port efficiency, reducing operating costs, and the manager who manages all operations at the port needs to check and respond quickly when delays of work and equipment support is needed. Based on the real-time location information confirmation of yard automation equipment used the existing system GPS, the real-time location information confirmation system is a GPS system of the tablet, rather than a port operation system that monitors location information for the entered information, depending on the completion of the task or the start of the task. Network configurations also reduce container processing delays by using commercial LTE services that do not have shading due to containers in the yard also reduce container processing delays. Trough introduction of smart devices using Android or IOS and container processing scheduling utilizing artificial intelligence, we will build a minimum delay system with Smart Device usage of container processing applications and optimization of container processing schedule. The adoption of smart devices and the minimization of container processing delays utilizing artificial intelligence are expected to improve the quality of port services by confirming the processing containers in real time to consumers who are container information demanders.

Efficient Implementation of NIST LWC SPARKLE on 64-Bit ARMv8 (ARMv8 환경에서 NIST LWC SPARKLE 효율적 구현)

  • Hanbeom Shin;Gyusang Kim;Myeonghoon Lee;Insung Kim;Sunyeop Kim;Donggeun Kwon;Seonggyeom Kim;Seogchung Seo;Seokhie Hong
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.33 no.3
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    • pp.401-410
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    • 2023
  • In this paper, we propose optimization methods for implementing SPARKLE, one of the NIST LWC finalists, on a 64-bit ARMv8 processor. The proposed methods consist of two approaches: an implementation using ARM A64 instructions and another using NEON ASIMD instructions. The A64-based implementation is optimized by performing register scheduling to efficiently utilize the available registers on the ARMv8 architecture. By utilizing the optimized A64-based implementation, we can achieve speeds that are 1.69 to 1.81 times faster than the C reference implementation on a Raspberry Pi 4B. The ASIMD-based implementation, on the other hand, optimizes data by parallelizing the ARX-boxes to perform more than three of them concurrently through a single vector instruction. While the general speed of the optimized ASIMD-based implementation is lower than that of the A64-based implementation, it only slows down by 1.2 times compared to the 2.1 times slowdown observed in the A64-based implementation as the block size increases from SPARKLE256 to SPARKLE512. This is an advantage of the ASIMD-based implementation. Therefore, the ASIMD-based implementation is more efficient for SPARKLE variant block cipher or permutation designs with larger block sizes than the original SPARKLE, making it a useful resource.

HW/SW Partitioning Techniques for Multi-Mode Multi-Task Embedded Applications (멀티모드 멀티태스크 임베디드 어플리케이션을 위한 HW/SW 분할 기법)

  • Kim, Young-Jun;Kim, Tae-Whan
    • Journal of KIISE:Computer Systems and Theory
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    • v.34 no.8
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    • pp.337-347
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    • 2007
  • An embedded system is called a multi-mode embedded system if it performs multiple applications by dynamically reconfiguring the system functionality. Further, the embedded system is called a multi-mode multi-task embedded system if it additionally supports multiple tasks to be executed in a mode. In this Paper, we address a HW/SW partitioning problem, that is, HW/SW partitioning of multi-mode multi-task embedded applications with timing constraints of tasks. The objective of the optimization problem is to find a minimal total system cost of allocation/mapping of processing resources to functional modules in tasks together with a schedule that satisfies the timing constraints. The key success of solving the problem is closely related to the degree of the amount of utilization of the potential parallelism among the executions of modules. However, due to an inherently excessively large search space of the parallelism, and to make the task of schedulabilty analysis easy, the prior HW/SW partitioning methods have not been able to fully exploit the potential parallel execution of modules. To overcome the limitation, we propose a set of comprehensive HW/SW partitioning techniques which solve the three subproblems of the partitioning problem simultaneously: (1) allocation of processing resources, (2) mapping the processing resources to the modules in tasks, and (3) determining an execution schedule of modules. Specifically, based on a precise measurement on the parallel execution and schedulability of modules, we develop a stepwise refinement partitioning technique for single-mode multi-task applications. The proposed techniques is then extended to solve the HW/SW partitioning problem of multi-mode multi-task applications. From experiments with a set of real-life applications, it is shown that the proposed techniques are able to reduce the implementation cost by 19.0% and 17.0% for single- and multi-mode multi-task applications over that by the conventional method, respectively.