• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.12
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• pp.1889-1893
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• 1990

In this paper, ultrasonic microscope system has been constructed with the small aperturre acoustic lens and the angle controller, and the new type of B-scanultransonic imaging has been analyzed. The system with small aperture lens was used to detect flaw existing within the thick specimen and its resolution was in the range of one wavelength at interior plane of sample. The anle controller was used to excited surface acoustic wave or shear wave. In order to obtain B-scan image of the flaw existig at interior of solids, shear wave has been excited and backscattering signals from the flaw have been processed. In experimental results, B-scan ultransonic images have been obtain from the flaws of varable shape and measured flaw size from the images has been in good agreement with practical size in the range of 10% error.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.1862-1865
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• 2005

We have a plan to design a controller for electron beam manufacturing system. At first, we designed a controller for SEM. The controller consists of five parts (power source, beam controller, scanning controller, optic controller and main controller). Beam controller supplies pulse wave for generating high voltage and can monitor the status of high voltage instrument through emission current. Optic controller controls focus, spot size and image shift. Main controller transmits variables from operating program to each part and monitors the status of peripheral device.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.180-188
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• 1999

${\mu}$-synthesis is applied to design a robust controller for a seeker scan loop system which has model uncertainty and is subject to a external disturbance due to abrupt missile maneuver. The issue of modelling a real-valued parametric uncertainty of a physical seeker scan loop system is discussed. The two-degree-of-frame control structure is employed to obtain better performance. It is shown that ${\mu}$-synthesis provides a superior framework for the robust control design of a seeker scan loop system which exhibits robust performance. The proposed robust control system satisfies design requirements, and especially shows good scanning performances for conical and rosette scan patterns despite parametric uncertainty in real system model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.54-61
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• 2003

In this paper, an efficient non-scan design-for-testability (DFT) method for controller circuits is proposed. The proposed method always guarantees a short test pattern generation time and complete fault efficiency. It has a lower area overhead than full-scan and other non-scan DFT methods and enables to apply test patterns at-speed. The proposed method also shortens the test application time through a test pattern re-ordering procedure. The efficiency of the proposed method is demonstrated using well known MCNC'91 FSM benchmark circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.74-79
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• 2006

Test Interface Controller (TIC) provided by ARM Ltd. is widely used for functional testing of System-on-Chip (SoC) adopting Advanced Microcontroller Bus Architecture (AMBA) bus system. Accordingly, this architecture has a deficiency of not being able to concurrently shifting in and out the structural scan test patterns through the TIC and AMBA bus. This paper introduces a new AMBA based Test Access Mechanism (ATAM) for speedy testing of SoCs embedding ARM cores. While preserving the compatability with the ARM TIC, since scan in and out operations can be performed simultaneously, test application time through the expensive Automatic Test Equipment (ATE) can be drastically reduced.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.8
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• pp.836-844
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• 1991

PLC(programmable logic controller) system is widely used for the control of factory. PLC system receives ladder diagram which is drawn by the user to implement hardware logic, converts the ladder diagram into sequence program which is executable in the PLC system, and executes the sequence program indefinitely unless user breaks. The sequence program processes the data of on/off signal, and endures 1 scan delay and missing of pulse-type signal shorter than a scan time. So, data dependency doesn't exist. By applying theis characteristics to multiprocessor architecture, we design parellel PLC functionally and evaluate performance upgrade. Parallel PLC consists of central processing module, N general processing unit, and a shared memory by master-slave type. Each module executes allocated sequence program by the control of central processing module. We can expect performance upgrade by parallel processing, and reliability by relocation of sequence program when error occurs in processing module.

• 제어로봇시스템학회:학술대회논문집
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• 1999.10a
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• pp.61-64
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• 1999

In this paper, a technique to expand the Input and Output (I/O) of the programmable logic controller (PLC) using remote I/O module is presented. The controller and the remote I/O module should have the same protocol and are interfaced through RS 485. Each remote I/O module consists of 16 digital input and 16 digital output, and the maximum of 32 remote I/O module can be linked to one controller. The remote I/O is programmed for interrupt request to controller independently. Therefore, there is no affect to the scan time of the controller. Using this technique, the PLC can be efficiently applied to the several hundred meters different control points such as the ON-OFF control fur the agriculture farm, the building automation system, a multi group of machine control.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2023-2030
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• 2010

In this paper, we present research results of developing high performance scan conversion unit and implementing it on FPGA chip. To increase performance of scan conversion unit, we propose an architecture of scan converter that is a SIMD architecture and uses tile-based traversing method. The proposed scan conversion unit can operate about 124Mhz clock frequency on Xilinx Vertex4 LX100 device. To verify the scan conversion unit, we also develop shader unit, texture mapping unit and $240{\times}320$ color TFT-LCD controller to display outputs of the scan conversion unit on TFT-LCD. Because the scan conversion unit implemented on FPGA has 311Mpixels/sec pixel rate, it is applicable to desktop pc's 3d graphics system as well as mobile 3d graphics system needing high pixel rates.

• ETRI Journal
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• v.30 no.3
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• pp.403-411
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• 2008

This paper introduces an interconnect delay fault test (IDFT) controller on boards and system-on-chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.