• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.8
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• pp.1172-1179
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• 2022

This paper describes a design of point scalar multiplier for public-key cryptography based on binary Edwards curves (BEdC). For efficient implementation of point addition (PA) and point doubling (PD) on BEdC, projective coordinate was adopted for finite field arithmetic, and computational performance was improved because only one inversion was involved in point scalar multiplication (PSM). By applying optimizations to hardware design, the storage and arithmetic steps for finite field arithmetic in PA and PD were reduced by approximately 40%. We designed two types of point scalar multipliers for BEdC, Type-I uses one 257-b×257-b binary multiplier and Type-II uses eight 32-b×32-b binary multipliers. Type-II design uses 65% less LUTs compared to Type-I, but it was evaluated that it took about 3.5 times the PSM computation time when operating with 240 MHz. Therefore, the BEdC crypto core of Type-I is suitable for applications requiring high-performance, and Type-II structure is suitable for applications with limited resources.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1221-1224
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• 2003

A 64-point R2$^2$ SDF pipeline FFT processor using a new efficient computation sharing multiplier was designed. Computation sharing multiplication specifically targets computation re-use in multiplication of coefficient vector by scalar and is effectively used in DSP(Digital Signal Processing). To reduce the number of multipliers in FFT, we used the proposed computation sharing multiplier. The 64-point pipeline FFT processor was implemented by VHDL and synthesized using Max+PLUSII of Altera. The simulation result shows that the proposed computation sharing multiplier can be reduced to about 17.8% logic cells compared with a conventional multiplier. This processor can operate at 33MHz and calculate a 64-point pipeline FFT in 1.94 $mutextrm{s}$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.176-184
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• 2005

In this paper, we implemented an Elliptic Curve Cryptography(ECC) processor for Digital Transmission Contents Protection (DTCP), which is a standard for protecting various digital contents in the network. Unlikely to other applications, DTCP uses ECC algorithm which is defined over GF(p), where p is a 160-bit prime integer. The core arithmetic operation of ECC is a scalar multiplication, and it involves large amount of very long integer modular multiplications and additions. In this paper, the modular multiplier was designed using the well-known Montgomery algorithm which was implemented with CSA(Carry-save Adder) and 4-level CLA(Carry-lookahead Adder). Our new ECC processor has been synthesized using Samsung 0.18 m CMOS standard cell library, and the maximum operation frequency was estimated 98 MHz, with the size about 65,000 gates. The resulting performance was 29.6 kbps, that is, it took 5.4 msec to process a 160-bit data frame. We assure that this performance is enough to be used for digital signature, encryption and decryption, and key exchanges in real time environments.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.246-248
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• 2022

Binary Edwards curves (BEdC), a new form of elliptic curves proposed by Bernstein, satisfy the complete addition law without exceptions. This paper describes an efficient hardware implementation of point scalar multiplication on BEdC using projective coordinates. Modified Montgomery ladder algorithm was adopted for point scalar multiplication, and binary field arithmetic operations were implemented using 257-bit binary adder, 257-bit binary squarer, and 32-bit binary multiplier. The hardware operation of the BEdC crypto-core was verified using Zynq UltraScale+ MPSoC device. It takes 521,535 clock cycles to compute point scalar multiplication.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.73-84
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• 2004

This paper suggests a new scalar multiplication algerian to resist SPA which threatens the security of cryptographic primitive on the hardware recently, and discusses how to apply this algerian Our algorithm is better than other SPA countermeasure algorithms aspect to computational efficiency. Since known SPA countermeasure algorithms have dependency of computation. these are difficult to construct parallel architecture efficiently. To solve this problem our algorithm removes dependency and computes a multiplication and a squaring during inversion with parallel architecture in order to minimize loss of performance. We implement hardware logic with VHDL(VHSIC Hardware Description Language) to verify performance. Synthesis tool is Synplify Pro 7.0 and target chip is Xillinx VirtexE XCV2000EFGl156. Total equivalent gate is 60,508 and maximum frequency is 30Mhz. Our scalar multiplier can be applied to digital signature, encryption and decryption, key exchange, etc. It is applied to a embedded-micom it protects SPA and provides efficient computation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.10a
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• pp.223-225
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• 2021

Modular multiplication is a key operation for point scalar multiplication of ECC, and is the most important factor affecting the performance of ECC processor. This paper describes a design of a 256-bit modular multiplier that adopts 3-way Toom-Cook multiplication algorithm and modified fast reduction algorithm. One 90-bit multiplier and three 264-bit adders were used to optimize the hardware size and the number of clock cycles required. The modular multiplier was verified by implementing it using Zynq UltraScale+ MPSoC device and the modular multiplication operation takes 15 clock cycles.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.773-776
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• 2003

This paper presents new hardware implementation of the ECC(Elliptic Curve Cryptography) algorithm that is improved in speed and stability. We proposed new datapath that changed square's position so that we can reduce required number of cycles for addition operation between two points by more than 30%. We used Massey-Omura parallel multiplier adopted Normal basis for fast scalar multiplications. Also the use of the window non-adjacent form (WNAF) method can reduce addition operation of each other different points. We implemented ECC system with GF($2^{196}$), and this system was designed and verified by VHDL.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.190-192
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• 2018

This paper describes a design of an elliptic curve cryptography (ECC) processor that supports five pseudo-random curves and five Koblitz curves over binary field defined by the NIST standard. The ECC processor adopts the Lopez-Dahab projective coordinate system so that scalar multiplication is computed with modular multiplier and XORs. A word-based Montgomery multiplier of $32-b{\times}32-b$ was designed to implement ECCs of various key lengths using fixed-size hardware. The hardware operation of the ECC processor was verified by FPGA implementation. The ECC processor synthesized using a 0.18-um CMOS cell library occupies 10,674 gate equivalents (GEs) and 9 Kbits RAM at 100 MHz, and the estimated maximum clock frequency is 154 MHz.

• ETRI Journal
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• v.21 no.1
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• pp.28-39
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• 1999

Koblitz has suggested to use "anomalous" elliptic curves defined over ${\mathbb{F}}_2$, which are non-supersingular and allow or efficient multiplication of a point by and integer, For these curves, Meier and Staffelbach gave a method to find a polynomial of the Frobenius map corresponding to a given multiplier. Muller generalized their method to arbitrary non-supersingular elliptic curves defined over a small field of characteristic 2. in this paper, we propose an algorithm to speed up scalar multiplication on an elliptic curve defined over a small field. The proposed algorithm uses the same field. The proposed algorithm uses the same technique as Muller's to get an expansion by the Frobenius map, but its expansion length is half of Muller's due to the reduction step (Algorithm 1). Also, it uses a more efficient algorithm (Algorithm 3) to perform multiplication using the Frobenius expansion. Consequently, the proposed algorithm is two times faster than Muller's. Moreover, it can be applied to an elliptic curve defined over a finite field with odd characteristic and does not require any precomputation or additional memory.

• Journal of IKEEE
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• v.25 no.1
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• pp.174-179
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• 2021

An Edwards curve cryptography (EdCC) core supporting point scalar multiplication (PSM) on Edwards curves of Edwards25519 and Edwards448 was designed. For area-efficient implementation, finite field multiplier based on word-based Montgomery multiplication algorithm was designed, and the extended twisted Edwards coordinates system was adopted to implement point operations without division operation. As a result of synthesizing the EdCC core with 100 MHz clock, it was implemented with 24,073 equivalent gates and 11 kbits RAM, and the maximum operating frequency was estimated to be 285 MHz. The evaluation results show that the EdCC core can compute 299 and 66 PSMs per second on Edwards25519 and Edwards448 curves, respectively. Compared to the ECC core with similar structure, the number of clock cycles required for 256-bit PSM was reduced by about 60%, resulting in 7.3 times improvement in computational performance.