• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권7호
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• pp.311-315
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• 2002

Chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD), inter-level dielectric (ILD) layers of multi-layer interconnections. In this paper, we studied the characteristics of polishing pad, which can apply shallow trench isolation (STI)-CMP process for global planarization of multi-level interconnection structure. Also, we investigated the effects of different sets of polishing pad, such as soft and hard pad. As an experimental result, hard pad showed center-fast type, and soft pad showed edge-fast type. Totally, the defect level has shown little difference, however, the counts of scratch was detected less than 2 on JR111 pad. Through the above results, we can select optimum polishing pad, so we can expect the improvements of throughput and device yield.

• 대한화학회지
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• 제48권1호
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• pp.39-45
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• 2004

산에 민감한 작용기를 갖는 tert-butyl methacrylate(tBMA)와 산 증식 기능을 갖는 4-hydroxy-4''p-styrenesulfonyloxyisopropylidene dicyclohexane(HSI)과 4-p-styrenesulfonyloxy-4''-tosyloxyisopropylidene dicyclohexane (STI)를 둘 다 함께 갖고 있는 공중합체를 새로운 고분자 산증식형 포토레지스트로 합성하였다. 산증식형 공중합체인 Poly(HSI-co-tBMA) film과 Poly(STI-co-tBMA) film은 산의 부재 시에는 레지스트 공정 온도에 대하여 충분한 열적 안정성을 나타내었다. Poly(STI-co-tBMA) film의 감도는 tBMA homopolymer에 비교하여 2배 정도 증진되었지만, Poly(HSI-co-tBMA) film은 오히려 2배 정도 감도가 저하되는 결과를 나타내었다. 고분자에 도입한 이러한 산증식 기능을 갖는 그룹의 구조에 따라 광감도 증진 효과가 다르게 나타남을 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.41-44
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• 2000

Ultra large scale integrated circuit(ULSI) & complementary metal oxide semiconductor(CMOS) circuits require gate electrode materials such as meta] silicides, titanium-silicide for gate oxides. Many previous authors have researched the improvements sub-micron gate oxide quality. However, little has been done on the electrical quality and reliability of ultra thin gates. In this research, we recommend novel shallow trench isolation structure and two step TiSi$_{2}$ formation for sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• KIEE International Transactions on Electrophysics and Applications
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• 제2C권5호
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• pp.262-267
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• 2002

In this paper, we first studied the factors affecting the motor current (MC) signal, which was strongly affected by the systematic hardware noises depending on polishing such as pad conditioning and arm oscillation of platen and recipe, head motor. Next, we studied the end point detection (EPD) for the chemical mechanical polishing (CMP) process of shallow trench isolation (STI) with reverse moat structure. The MC signal showed a high amplitude peak in the fore part caused by the reverse meal. pattern. We also found that the EP could not be detected properly and reproducibly due to the pad conditioning effect, especially when conventional low selectivity slurry was used. Even when there was no pad conditioning effect, the EPD method could not be applied, since the measured end points were always the same due to the characteristics of the reverse moat structure with an open nitride layer.

• KIEE International Transactions on Electrophysics and Applications
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• 제3C권1호
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• pp.28-32
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• 2003

In this paper, we have studied the in-situ end point detection (EPD) for direct chemical mechanical polishing (CMP) of shallow trench isolation (STI) structures without the reverse moat etch process. In this case, we applied a high selectivity $1n (HSS) that improves the silicon oxide removal rate and maximizes oxide to nitride selectivity Quite reproducible EPD results were obtained, and the wafer-to-wafer thickness variation was significantly reduced compared with the conventional predetermined polishing time method without EPD. Therefore, it is possible to achieve a global planarization without the complicated reverse moat etch process. As a result, the STI-CMP process can be simplified and improved using the new EPD method.

• 대한전자공학회논문지SD
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• 제39권5호
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• 한국경영과학회:학술대회논문집
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• 대한산업공학회/한국경영과학회 2002년도 춘계공동학술대회
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• pp.686-692
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• 2002

Disassembly scheduling is the problem of determining the ordering and disassembly schedules of used products while satisfying the demand of their parts of components over a certain planning horizon. The objective is to minimize the sum of purchase, setup, disassembly operation and inventory holding costs. This paper considers products with assembly structure, i.e. products without parts commonality, and suggests a heuristic in which an initial solution is obtained in the form of the minimal latest disassembly schedule, and then improved considering trade-offs among different cost factors. To show the performance of the heuristic suggested in this paper, computational experiments were done on the modified existing examples and the results show that the heuristic can give optimal of very near optimal solutions within very short computation times.

• 기술혁신학회지
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• 제14권2호
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• pp.246-259
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• 2011

시장구조와 혁신의 가치간 관계를 구명하는 것은 경쟁과 STI 정책수행에 중요하다. 만일 혁신의 가치가 특정 시장구조에서 상승된다면 정부는 해당 산업의 시장구조를 변화시킬 수 있다. 선형수요와 고정된 한계비용의 경우, 꾸르노 경쟁에서의 major와 minor 기술혁신에 대한 인센티브가 합병과 공동 연구개발의 경우보다 더 작다는 결과를 단순한 캘리브레이션을 통해 도출할 수 있다. 이는 또다시 독점이 필요악임을 시사한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.421-424
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• 2004

As the deep sub-micron devices are recently integrated high package density, novel process method for sub $0.1{\mu}m$ devices is required to get the superior thin gate oxide characteristics and reliability. However, few have reported on the electrical quality and reliability on the thin gate oxide. In this paper I will recommand a novel shallow trench isolation structure for thin gate oxide $30{\AA}$ of deep sub-micron devices. Different from using normal LOCOS technology, novel shallow trench isolation have a unique 'inverse narrow channel effects' when the channel width of the devices is scaled down shallow trench isolation has less encroachment into the active device area. Based on the research, I could confirm the successful fabrication of shallow trench isolation(STI) structure by the SEM, in addition to thermally stable silicide process was achiever. I also obtained the decrease threshold voltage value of the channel edge and the contact resistance of $13.2[\Omega/cont.]$ at $0.3{\times}0.3{\mu}m^2$. The reliability was measured from dielectric breakdown time, shallow trench isolation structure had tile stable value of $25[%]{\sim}90[%]$ more than 55[sec].

• 한국정보통신학회논문지
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• 제16권1호
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• pp.127-132
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• 2012

본 논문에서는, 초고집적 MOSFET를 위한 향상된 얕은 트랜치 접합 격리에서 높은 임계전압을 위한 활성영역 부분의 제안된 구조의 가장자리 효과를 시뮬레이션 하였다. 얕은 접합 격리는 트랜지스터와 트랜지스터 사이에서 전기적 격리를 하기 때문에 쌍보형-모스 기술에서 중요한 공정 요소이다. 시뮬레이션 결과, 얕은 트랜치 접합 격리 구조가 수동적인 전기적 기능 일지라도, 소자의 크기가 감소됨에 따라서, 초대규모 집적회로 공정의 응용에서 제안된 얕은 트랜치 격리 구조에서 전기적 특성의 영향은 전위차, 전계와 포화 임계 전압에서 높게 나타났다.