• 센서학회지
• /
• 제3권1호
• /
• pp.5-11
• /
• 1994

본 논문은 실리콘기판 직접접합기술과 에피택샬 성장법으로 각각 형성한 SOI구조, 즉 Si/$SiO_{2}$/Si 및 Si/$Al_{2}O_{3}$/Si 상에 제작한 압저항형 압력센서의 특성을 기술한다. SOI구조의 절연층을 압저항의 유전체 분리막으로 이용한 압력센서는 $300^{\circ}C$ 까지 사용 가능했다. SOI구조의 절연층을 박막 실리콘 다아어프램 형성시 에칭 중지막으로 이용한 경우, 제작된 압력센서의 200개 소자들에 대한 압력감도의 변화는 ${\pm}2.3%$ 이내로 제어 가능했다. 더구나 실리콘 기판 직접접합기술과 에피택샬 성장법의 결합으로 형성한 더불 SOI구조($Si/Al_{2}O_{3}/Si/SiO_{2}/Si$)상에 제작된 압력센서는 고온분위기에서 사용 가능할 뿐만 아니라 고분해 능력을 갖는 특성을 보였다.

• 센서학회지
• /
• 제1권2호
• /
• pp.131-145
• /
• 1992

본 논문은 SOI트랜스듀서 및 회로를 위해, Si 직접접합과 M-C국부연마법에 의한 박막SOI구조의 형성 공정을 기술한다. 또한, 이러한 박막SOI의 전기적 및 압저항효과 특성들을 SOI MOSFET와 cantilever빔으로 각각 조사했으며, bulk Si에 상당한다는 것이 확인되었다. 한편, SOI구조를 이용한 두 종류의 압력트랜스듀서를 제작 및 평가했다. SOI구조의 절연층을 압저항의 유전체분리층으로 이용한 압력트랜스듀서의 경우, $-20^{\circ}C$에서 $350^{\circ}C$의 온도범위에 있어서 감도 및 offset전압의 변화는 자각 -0.2% 및 +0.15%이하였다. 한편, 절연층을 etch-stop막으로 이용한 압력트랜스듀서에 있어서의 감도변화를 ${\pm}2.3%$의 표준편차 이내로 제어할 수 있다. 이러한 결과들로부터 개발된 SDB공정으로 제작된 SOI구조는 집적화마이크로트랜스듀서 및 회로개발에 많은 장점을 제공할 것이다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권6호
• /
• pp.712-717
• /
• 2014

The performance of npn SiGe HBT on thin film SOI is investigated at 32 nm technology node by applying body bias. An n-well is created underneath thin BOX to isolate the body biased SOI HBT from SOI CMOS. The results show that the HBT voltage gain and power gain can be programmed by applying body bias to the n-well. This HBT can be used in variable gain amplifiers that are widely used in the receiver chain of RF systems. The HBT is compatible with 32 nm FDSOI technology having 10 nm film thickness and 30 nm BOX thickness. As the breakdown voltage increases by applying the body bias, the SOI HBT with 3 V $V_{CE}$ has very high $f_tBV_{CEO}$ product (839 GHzV). The self heating performance of the proposed SOI HBT is studied. The high voltage gain and power gain (60 dB) of this HBT will be useful in designing analog/RF systems which cannot be achieved using 32 nm SOI CMOS (usually voltage gain is in the range of 10-20 dB).

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1994년도 춘계학술대회 논문집
• /
• pp.145-146
• /
• 1994

A SOI technology is promising for micromachining: high temperature operation, the fabrication easiness of sophisticated and 3D microstructures, radiation hardness, integrated sensors etc. This paper describes reviews of SOI technologies, and their applications microsensors and microactuators

• 한국재료학회지
• /
• 제15권9호
• /
• pp.613-619
• /
• 2005

The ever increasing popularity and acceptance in the market place of portable systems, such as cell phones, PDA, notebook PC, etc., are fueling effects in further miniaturizing and lowering power consumption in these systems. The dynamic power consumption due to the CPU activities and the static power consumption due to leakage currents are two major sources of power consumption. Smaller devices and a lower de voltage lead to reducing the power requirement, while better insulation and isolation of devices lead to reducing leakage currents. All these can be harnessed in the SOI (silicon-on-insulator) technology. In this study, the key aspects of the SOI technology, mainly device electrical properties and device processing steps, are briefly reviewed. The interesting materials issues, such as SOI structure formation and SOI wafer fabrication methods, are then surveyed. In particular, the recent technological innovations in two major SOI wafer fabrication methods, namely wafer bonding and SIMOX, are explored and compared in depth. The results of the study are nixed in that, although the quality of the SOI structures has shown great improvements, the processing steps are still found to be too complex. Between the two methods, no clear winner has yet emerged in terms of the product quality and cost considerations.

• 대한전자공학회논문지SD
• /
• 제41권4호
• /
• pp.9-14
• /
• 2004

매몰 산화층 밑의 실리콘 기판에 자기정렬 방법으로 ground plane 전극을 만든 SOI MOSFET의 단채널 현상과 Punchthrough 특성을 측정·분석하였다. 채널 길이가 $0.2{\mu}m$ 이하의 소자에서는 GP-SOI 소자가 FD-SOI 소자보다 채널 길이에 따른 문턱전압 저하 및 subthreshold swing이 작고 DIBL 현상이 크게 개선됨을 알 수 있었다. 기판전압에 따른 문턱전압 특성으로부터 GP-SOI 소자의 body factor가 FD-SOI 소자보다 큰 것을 알 수 있었다. 그리고 punchthrough 전압 특성으로부터 GP-SOI 소자의 punchthrough 전압이 FD-SOI 소자보다 큰 것을 알 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권3호
• /
• pp.274-283
• /
• 2014

In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved $f_tBV_{CEO}$ product (397 GHzV). As the $BV_{CEO}$ value is higher for low value of epi layer doping, higher supply voltage can be used to increase the $f_t$ value of the HBT. At 1.8 V $V_{CE}$, the $f_tBV_{CEO}$ product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV $f_tBV_{CEO}$ product at 1.2 V $V_{CE}$). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

• E2M - 전기 전자와 첨단 소재
• /
• 제8권2호
• /
• pp.165-170
• /
• 1995

This paper describes the fabrication and characteristics of a Si Hall sensor fabricated on a SOI (Si-on-insulator) structure. The SOI structure was formed by SDB(Si-wafer direct bonding) technology and the insulator of the SOI structure was used as the dielectrical isolation layer of a Hall sensor. The Hall voltage and sensitivity of the implemented SDB SOI Hall sensors showed good linearity with respect to the applied magnetic flux density and supplied current. The product sensitivity of the SDB SOI Hall sensor was average 600V/A.T and its value has been increased up to 3 times compared to that of bulk Si with buried layer of 10.mu.m. Moreover, this sensor can be used at high-temperature, high-radiation and in corrosive environments.

• 한국전기전자재료학회논문지
• /
• 제15권7호
• /
• pp.583-590
• /
• 2002

In this paper, a new Silicon on Insulator (SOI)-based photodetector was proposed, and its basic operation principle was explained. Fabrication steps of the detector are compatible with those of conventional SOI CMOS technology. With the proposed structure, RGB (Read, Green, Blue) which are three primary colors of light can be realized without using any organic color filters. It was shown that the characteristics of the SOI-based detector are better than those of bulk-based detector. To see the response characteristics to the green (G) among RGB, SOI and bulk NMOSFETS were fabricated using $1.5\mu m$ CMOS technology and characterized. We obtained optimum optical response characteristics at $V_{GS}=0.35 V$ in NMOSFET with threshold voltage of 0.72 V. Drain bias should be less than about 1.5 V to avoid any problem from floating body effect, since the body of the SOI NMOSFET was floated. The SOI and the bulk NMOSFETS shown maximum drain currents at the wavelengths of incident light around 550 nm and 750 nm, respectively. Therefore the SOI detector is more suitable for the G color detector.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1994년도 추계학술대회 논문집
• /
• pp.86-89
• /
• 1994

This paper describes the fabrication and basic characteristics of a Si Hall device fabricated on a SOI(Si-on-insulator) structure. In which SOI structure was formed by SOB(Si-wafer direct bonding) technology and the insulator of the SOI structure was used as the dielectrical isolation layer of a Hall device. The Hall voltage and sensitivity of the implemented SDB SOI Hall devices showed good linearity with respectivity to the applied magnetic flux density and supple iud current. The product sensitivity of the SDB SOI Hall device was average 670 V/A$.$T and its value has been increased up to 3 times compared to that of bulk Si with buried layer of 10$\mu\textrm{m}$. Moreover, this device can be used at high-temperature, high-radiation and in corrosive environments.