• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.126-127
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• 2008

The effects annealing conditions on the electrical conductions of SOI substrate were studied. The reversible change of resistance and carrier concentration in accordance with the annealing temperature were observed for the first time in SOI substrate. The thermal donors due to interstitial oxygen atoms contribute the change of resistance and carrier concentration. Final1y, we show that the furnace annelaing at $500^{\circ}C$ at final heat treatment stage is effective for eliminate the thermal donor effects in SOI substrate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.126-129
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• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method, and this process was found to be very accurate method for SOI thickness control. During electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential (OCP) point, the passivation potential (PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.5
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• pp.431-436
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• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method and this process was found to be a very accurate method for SOI thickness control. During electrochemical etch-stop leakage current versus voltage curves were measured for analysis of the open current potential(OCP) point the passivation potential(PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.9-14
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• 2004

This paper reports the measurement and analysis of the short channel effects and the punchthrough voltage of SOI-MOSFET with a self-aligned ground plane electrode in the silicon mechanical substrate underneath the buried oxide. When the channel length is reduced below 0.2${\mu}{\textrm}{m}$ it is observed that the threshold voltage roll-off and the subthreshold swing with channel length are reduced and DIBL is improved more significantly in GP-SOI devices than FD-SOI devices. It is also observed from the dependence of threshold voltage with substrate biases that the body factor is a higher in GP-SOI devices than FD-SOI devices. From the measurement results of punchthrough voltage, GP-SOI devices show the higher punchthrough voltages than FD-SOI devices

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.706-710
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• 2008

The substrate bias effect on the current level of SOI-MOSFETs for high temperature operation has been investigated. In this work, we demonstrate the current level of SOI-MOSFETs can be controlled at different temperatures by applying a control bias to the substrate, showing that all current levels below T=150$^{\circ}C$ can be adjusted to a constant current level. 2D numerical simulation results show that substrate bias effectively controls the current conduction; as the substrate bias effectively lower the potential of the channel, inversion carrier generation is effectively controlled and consequently a constant current conduction level is achieved up to T=150$^{\circ}C$. We also demonstrate that the device simulated in this work has same operation at any temperature below T=150$^{\circ}C$ through mixed mode simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.11
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• pp.1000-1004
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• 2006

In this paper, thermal stability of Ni-silicide formed on the SOI substrate with $B_{11}$ has been characterized. The sheet resistance of Ni-silicide on un-doped SOI and $B_{11}$ implanted bulk substrate was increased after the post-silicidation annealing at $700^{\circ}C$ for 30 min. However, in case of $B_{11}$ implanted SOI substrate, the sheet resistance showed stable characteristics after the post-silicidation annealing up to $700^{\circ}C$ for 30 min. The main reason of the excellent property of $B_{11}$ sample is believed to be the retardation of Ni diffusion by the boron and bottom oxide layer of SOI. Therefore, retardation of Ni diffusion is highly desirable lot high performance Ni silicide technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.569-572
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• 2000

This paper presents the optimized fabrication and thermal characteristics of micro-heaters for thermal MEMS applications using a SDB SOI substrate. The micro-heater is based on a thermal measurement principle and contains for thermal isolation regions a 10$\mu\textrm{m}$ thick silicon membrane with oxide-filled trenches in the SOI membrane rim. The micro-heater was fabricated with Pt-RTD(Resistance Thermometer Device)on the same substrate by using MgO as medium layer. The thermal characteristics of the micro-heater with the SOI membrane is 280$^{\circ}C$ at input Power 0.9 W; for the SOI membrane with 10 trenches, it is 580$^{\circ}C$ due to reduction of the external thermal loss. Therefore, the micro-heater with trenches in SOI membrane rim provides a powerful and versatile alternative technology for improving the performance of micro thermal sensors and actuators.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.301-306
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• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method, and this process was found to be a very accurate method for SOI thickness control. During electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential(OCP) point, the passivation potential(PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.24-25
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• 2006

In this study, Ni silicide on the SOI substrate doped B11 is proposed to improve thermal stability. The sheet resistance of Ni-silicide utilizing pure SOI substrate increased after the post-silicidation annealing at $600^{\circ}C$ for 30 min. However, using the proposed B11 implanted substrate, the sheet resistance showed stable characteristics after the post-silicidation annealing up to $700^{\circ}C$ for 30 min.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.95-96
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• 2009

A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.