• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.113-114
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• 2015

본 논문은, 태양광 및 차세대 이동수단에 적용되는 리튬-이온 전지의 전기적 모델링를 수행하였다. 전지의 전기적 모델링을 통하여 충 방전 특성, 용량, 개방 전압, 내부 저항과 같은 전지의 특성을 모의함으로써, 다양한 환경에서 어플리케이션에 적용할 전지를 테스트해 볼 수 있다. 리튬-이온 전지는 LGD 18650 B4(2,600mAh) 모델을 사용하였으며, 실험과 시뮬레이션을 통하여 설계된 모델의 타당성을 검증한다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.5
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• pp.37-47
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• 2004

The security of personal informations has been an important issue since the field of smart card applications has been expanded explosively. The security of smart card is based on cryptographic algorithms, which are highly required to be implemented into hardware for higher speed and stronger security. In this paper, a SEED cryptographic processor is designed by employing one round key generation block which generates 16 round keys without key registers and one round function block which is used iteratively. Both the round key generation block and the F function are using only one G function block with one 5${\times}$l MUX sequentially instead of 5 G function blocks. The proposed SEED processor has been implemented such that each round operation is divided into seven sub-rounds and each sub-round is executed per clock. Functional simulation of the proposed cryptographic processor has been executed using the test vectors which are offered by Korea Information Security Agency. In addition, we have evaluated the proposed SEED processor by executing VHDL synthesis and FPGA board test. The die area of the proposed SEED processor decreases up to approximately 40% compared with the conventional processor.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.61-71
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• 2014

As the occupancy rate of the flash memory increases in the storage media market for the embedded system and the semi-conductor industry grows, the demand and supply of flash memory is increasing by a big margin. They are especially used in large quantity in the smart phones, tablets, PC, SSD and Soc(System on Chip) etc. The flash memory is divided into the NOR type and NAND type according to the cell arrangement structure and the NAND type is divided into the SLC(Single Level Cell) and MLC(Multi Level Cell) according to the number of bits that can be stored in each cell. Many tests have been performed on NOR type such as BIST(Bulit-In Self Test) and BIRA(Bulit-In Redundancy Analysis) etc, but there is little study on the NAND type. For the case of the existing BIST, the test can be proceeded using external equipments like ATE of high price. However, this paper is an attempt for the improvement of credibility and harvest rate of the system by proposing the BIST for the MLC NAND type flash memory of Finite State Machine structure on which the pattern test can be performed without external equipment since the necessary patterns are embedded in the interior and which uses the MLC NAND March(x) algorithm and pattern which had been proposed for the MLC NAND type flash memory.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.185-191
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• 2006

DSRC((Dedicated Short Range Communication) is dedicated short range communication for wireless communications between RSE(Road Side Equipment) and OBE(On-Board Unit) within vehicle moving high speed. In this paper, we implemented 5.8GHz DSRC modem according to Korea TTA(Telecommunication Technology Association) standard and investigated implementation results and design process for SoC(System on a Chip) embedding ARM CPU which control overall signal and process arithmetic work. The SoC is implemented by 0.11um design technology and 480pins EPBGA package. In the implemented SoC ($Jaguar^{TM}$), 5.8GHz DSRC PHY(Physical Layer) modem and MAC are designed and included. For CPU core ARM926EJ-S is embedded, and LCD controller, smart card controller, ethernet MAC, and memory controller are designed as main function.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.30-36
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• 2010

In recent memories, repair is an unavoidable method to maintain its yield and quality. Although many word oriented memories as well as embedded memories in system-on-chip (SOC) consists of multiple local memory blocks with a global spare architecture, most of previous studies on built-in redundancy analysis (BIRA) algorithms have focused on single memory block with a local spare architecture. In this paper, a new BIRA algorithm for multiple blocks with a global spare architecture is proposed. The proposed BIRA is basd on CRESTA which is able to achieve optimal repair rate with almost zero analysis time. In the proposed BIRA, all repair solutions for local memory blocks are analyzed by local analyzers which belong to each local memory block and then compared sequentially and judged whether each solution can meet the limitation of the global spare architecture or not. Experimental results show that the proposed BIRA achieves much faster analysis speed compared to previous BIRAs with an optimal repair rate.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.11
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• pp.5357-5365
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• 2013

In this paper, we propose that a model based design for a electric tractor system by using ASM(Automotive Simulation Models). Before developing a realistic electric tractor, it is essential that defining the capacities of power sources and optimizing the parameters of electric tractor. In additionally, because the electric tractor must have not only driving function but also working function, two PMSM are used at electric tractor. ASM which is based on simulink and Carsim were used to design a electric system and powertrain of electric tractor. For verifying the electric tractor system, we compared the design parameters such as max power, state of charge, drive distance, velocity which were carried out by the simulation and experimental method. The predicted results by the development model were in good agreement with the simulation results. According to simulation of tractor, it is possible to arrange the advanced research of dynamical characteristic of tractor and present the guidelines for the electrical driving system.

• The KIPS Transactions:PartB
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• v.17B no.1
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• pp.47-54
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• 2010

Old archived film shows two major defects: line scratch and blobs. In this paper, we present a design and implementation of an automatic video restoration system for line scratches observed in archived film. We use autoregressive (AR) image model because we can make stochastic and specifically autoregressive image generation process with our PAST-PRESENT model and Sampling Pattern. We designed locality maximizing scanning pattern, which can generate nearly stationary time-like series of pixels, which is a strong requirement for a stochastic series to be autoregressive. The sampled pixel series undergoes filtering and model fitting using Durbin-Levinson algorithm before interpolation process. We designed three-stage film restoration system, which includes (1) film acquisition from VHS tapes, (2) simple line scratch detection and restoration, and (3) manual blob identification and sophisticated inpainting scheme. We implemented film acquisition and simple inpainting scheme on Texas Instruments DSP board TMS320DM642 EVM, and implemented our AR inpainting scheme on PC for sophisticated restoration. We experimented our scheme with two old Korean films: "Viva Freedom" and "Robot Tae-Kwon-V", and the experimental results show that our scheme improves Bertalmio's scheme for subjective quality (MOS), objective quality (PSNR), and especially restoration ratio (RR), which reflects how much similar to the manual inpainting results.