• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1633-1640
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• 2006

The problem of reducing power dissipation while simultaneously delivering acceptable levels of performance is becoming a critical concern in high pelf[mann system design. In this paper, we present this power dissipation problem from the clock generation and distribution side. We examine clock power efficiency and several applications as well as wireless communication circuits.

• Proceedings of the Korean Society of Computer Information Conference
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• 2014.01a
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• pp.9-13
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• 2014

The performance of large scale software applications has been automatically increasing for last few decades under the influence of Moore's law - the number of transistors on a microprocessor roughly doubled every eighteen months. However, on-chip transistors limitations and heating issues led to the emergence of multicore processors. The energy efficient ARM based System-on-Chip (SoC) processors are being considered for future high performance computing systems. In this paper, we present a case study of two widely used parallel programming models i.e. MPI and MapReduce on distributed memory cluster of ARM SoC development boards. The case study application, Black-Scholes option pricing equation, was parallelized and evaluated in terms of power consumption and throughput. The results show that the Hadoop implementation has low instantaneous power consumption that of MPI, but MPI outperforms Hadoop implementation by a factor of 1.46 in terms of total power consumption to execution time ratio.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.391-393
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• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.500-502
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• 2003

In this paper, we have designed a platform with MSC8101 processor for networked converter monitoring and diagnosis. MSC8101 is a dual processor type SOC(System On a Chip), which is consist of 16bit DSP and 32bit RISK CPM. As it have DSP and CPM, MSC8101 is competent for networking and data processing application. This MSC8101 platform is designed for networked monitoring and diagnosis, so it is important processing ability and networking capability.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1067.1-1067.4
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• 2000

During the last three decades power electronics has gone through energetic technical evolution. The technical needs from wide area such as in industrial, commercial, consumer, aerospace and environmental applications have driven the environment favorably for the power electronics. In the future, two extreme technology-expansion trends are expected: one into low power, and the other into very high power. The former is based on the high frequency and the circuit miniature using VLSI circuit and surface mounting aiming for the system-on-chip (SOC) technology. The latter includes the application areas of power utility such as HVDC, FACTS and SVC and large science area of electrophsycal apparatus such as thermonuclear fusion, acclerators, and electric guns. This paper describes the technology status of some major elements which are available today and the key roles of the power electronics from view points of applications. The author would like to take this opportunity to raise discussions about the future technology development trend of power electronics in our country with the fellow power electronics engineers.

• IT SoC Magazine
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• s.2
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• pp.34-38
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• 2004

실리콘 처리 기술의 고속화 요구와 유무선 환경에서 동영상 통신이 가능한 비디오 폰, 영상 회의 시스템, 이동 통신용 단말기 등의 전자 제품 사용자의 급증은 시스템을 하나의 칩에 집적화하는 SoC(System-On-a-Chip) 설계 기술을 요구하고 있다. 칩의 복잡도와 SoC 제품의 생산성 차이가 계속적으로 증가함에 따라 현재의 IC 설계 방법으로는 SoC 제품의 성능과 요구의 변화를 만족시킬 수 없다. 칩의 면적을 최소화하고 성능을 최대화하며 게이트 수준의 최적화를 통한 기존의 셀 기반 설계 방법으로는 설계의 생산성 문제를 해결할 수 없다. 이러한 문제를 해결 위한 새로운 설계 방법인 IP 재사용을 기반으로 한 플랫폼 기반 설계가 제시되었다. 플랫폼 기반 설계는 SoC 제품을 빠르게 개발하기 위한 응용 기반 통합 플랫폼과 재사용이 가능한 IP(Intellectual Property) 이용한 플랫폼 기반 설계(Platform-Based Design) 방법이다. 새로운 설계 방법은 90% 이상의 IP 재사용을 통해서 설계 시간을 단축하며, 시스템 수준에서의 최적화를 통해서 제품의 시장 경쟁력(Time-to-Market)의 문제를 해결하기 위한 방법이다.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.133-134
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• 2015

최근 전자기술이 발달함에 따라, 전자기기의 집적도가 높아지고 있으며, 그에 따라 전자기적 간섭(Electromagnetic Interference)이 큰 문제로 대두되고 있다. 특히, 집적도가 높은 스마트 기기(Smart Device)의 AP(Applicaton Processor)의 경우, 여러 기능을 수행하는 부품이 집적된 SOC(System On Chip)이기 때문에, 전자기적 간섭에 더 민감할 수 있다. 더불어 LTE(Long Term Evolution)을 무선통신으로 이용하는 다양한 주파수대에서 전자기적 간섭은 어플리케이션 및 전자기기의 오작동을 초래할 수 있다. 이를 해결하기 위하여 본 논문에서는 칩패캐지 레벨의 Meander 구조의 기존 필터(Filter)가 가진 문제점을 해결한 구조를 설계하여 3차원 상의 전자장 시뮬레이션을 수행하였다. 또한, 칩의 내성(Immunity)이 취약한 여러 주파수 범위를 차단할 수 있는 이 중 대역차단 필터(Dual Band Stop Filter)를 Meader Line구조를 단순하게 만들어 설계하고 그에 따른 결과를 분석하였다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.3
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• pp.129-134
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• 2020

Moisture infiltration inside the solar cell module, filling of EVA sheet, melting of the frame seal, and deterioration of power generation performance in the module one year after installation are occurring. Whitening phenomenon, electrode corrosion phenomenon, and dielectric breakdown phenomenon are appearing in solar cell module installed in Korea before 5-7 years, leading to deterioration of power generation performance, and big problems for long-term reliability and long life technology are emerging. Therefore, in order to solve these problems, the development of a micro inverter (MiCrco Inverter Converter, MiC) including the function of securing the durability of the solar cell module and monitoring the aging progress and the solar cell based on the monitoring data from the MiC smart monitoring programs have been proposed to determine the aging of modules. In addition, in order to become a highly efficient solar smart monitoring system through systematic operation management through IT convergence with MiC that has enhanced monitoring function of solar cell module, SoC(System On Chip) in micro inverter is the environment for solar cell module. There is a demand for functions that can detect information in a complex manner and perform communication and control when necessary. Based on these requirements, this paper aims to develop SoC-based low-cost MiC smart photovoltaic system technology.

• Journal of Practical Engineering Education
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• v.8 no.2
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• pp.111-120
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• 2016

Education equipment for field programmable gate array (FPGA) design of sensor-based IOT (Internet Of Thing) system is introduced. Because sensors have different interfaces, several types of interface controller on FPGA need. Using this equipment, several types of interface controller, which can control ADC (analog-to-digital converter) for analog sensor outputs and $I^2C$ (Inter-Integrated Circuit), SPI (Serial Peripheral Interface Bus), and GPIO (General-Purpose Input/Output) for digital sensor outputs, can be designed on FPGA. Image processing hardware using image sensors and display controller for real and image-processed images or videos can be design on FPGA chip. This equipment can design a SOC (System On Chip) consisting of a hard process core on Linux OS and a FPGA block for IOT system which can communicate with wire and wireless networks. Using the education equipment, an example of hardware design using image sensor and accelerometer is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.30-36
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• 2010

In recent memories, repair is an unavoidable method to maintain its yield and quality. Although many word oriented memories as well as embedded memories in system-on-chip (SOC) consists of multiple local memory blocks with a global spare architecture, most of previous studies on built-in redundancy analysis (BIRA) algorithms have focused on single memory block with a local spare architecture. In this paper, a new BIRA algorithm for multiple blocks with a global spare architecture is proposed. The proposed BIRA is basd on CRESTA which is able to achieve optimal repair rate with almost zero analysis time. In the proposed BIRA, all repair solutions for local memory blocks are analyzed by local analyzers which belong to each local memory block and then compared sequentially and judged whether each solution can meet the limitation of the global spare architecture or not. Experimental results show that the proposed BIRA achieves much faster analysis speed compared to previous BIRAs with an optimal repair rate.