• Smart Media Journal
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• v.10 no.3
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• pp.31-38
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• 2021

It is hard to predict when and where a fall accident will happen. Also, if rapid follow-up measures on it are not performed, a fall accident leads to a threat of life, so studies that can automatically detect a fall accident have become necessary. Among automatic fall-accident detection techniques, a fall detection scheme using an IMU (inertial measurement unit) sensor attached to a wrist is difficult to detect a fall accident due to its movement, but it is recognized as a technique that is easy to wear and has excellent accessibility. To overcome the difficulty in obtaining fall data, this study proposes an algorithm that efficiently learns less data through machine learning such as KNN (k-nearest neighbors) and SVM (support vector machine). In addition, to improve the performance of these mathematical classifiers, this study utilized feature data aquired in the frequency space. The proposed algorithm analyzed the effect by diversifying the parameters of the model and the parameters of the frequency feature extractor through experiments using standard datasets. The proposed algorithm could adequately cope with a realistic problem that fall data are difficult to obtain. Because it is lighter than other classifiers, this algorithm was also easy to implement in small embedded systems where SIMD (single instruction multiple data) processing devices were difficult to mount.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.2 s.308
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• pp.1-11
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• 2006

In this paper, we propose a new register file architecture called the Register File Extension for Multi-words or Long-word Operation (RFEMLO) to accelerate both symmetric and asymmetric cryptographic algorithms. Based on the idea that most of cryptographic algorithms heavily use multi-words or long-word operations, RFEMLO allows multiple contiguous registers to be specified as a single operand. Thus, a single instruction can specify a SIMD-style multi-word operation or a long-word operation. RFEMLO can be applied to general purpose processors by adding instruction set for multi-words or long-word operands and functional units for additional instruction set. To evaluate the performance of RFEMLO, we use Simplescalar/ARM 3.0 (with gcc 2.95.2) and run detailed simulations on various symmetric and asymmetric cryptographic algorithms. By applying RFEMLO, we could get maximum 62% and 70% reductions in the total instruction count of symmetric and asymmetric cryptographic algorithms respectively. Also, performance results show that a speedup of 1.4 to 2.6 can be obtained in symmetric cryptographic algorithms and a speedup of 2.5 to 3.3 can be obtained for asymmetric cryptographic algorithms when we apply RFEMLO to a processor with an in-order pipeline. We also found that RFEMLO can effectively improve the performance of these cryptographic algorithms with much less cost compared to issue-width increase available in Superscalar implementations. Moreover, the RFEMLO can also be applied to Superscalar processor, leading to additional 83% and 138% performance gain in symmetric and asymmetric cryptographic algorithms.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.11a
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• pp.136-137
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• 2010

본 논문에서는 고속, 저전력 비디오 부호화에 적합한 변환영역 Wyner-Ziv 분산비디오부호화기를 더욱 고속화하기 위한 병렬처리 방법을 제안한다. 기존에는 변환영역 Wyner-Ziv 분산비디오부호화를 위해 양자화 정보를 비트플레인단위로 분해후 이를 순차적으로 LDPCA 부호화하여 전체 부호화기 연산량에서 LDPCA의 복잡도가 약 54% 정도 차지하였고, 이는 고비트율로 부호화 할수록 더욱 증가하였다. 제안방법은 이를 개선하기 위해 여러 개의 비트플레인을 하나의 심벌 (symbol)로 묶어서 LDPCA 부호화를 수행하여 한 번의 연산으로 여러 개의 데이터를 동시에 처리할 수 있게 한다. 일종의 단일 명령 복수 데이터 처리 (SIMD, Single instruction, multiple data)에 의한 고속화 방법이다. 이를 통해 제안방법은 기존의 순차적 처리 방법에 비해 저비트율에서는 8배, 고비트율에서는 55배까지 LDPCA의 부호화 속도를 향상시켰다. 결과적으로 전체 부호화에서 LDPCA의 상대적인 복잡도 비율은 4%정도로 낮아지게 되었으며 Wyner-Ziv 영상의 부호화 속도도 약 1.5 ~ 2배까지 향상되었다. 제안방법은 LDPCA를 사용하는 다른 Wyner-Ziv 분산비디오부호화 구조에도 적용 가능할 것으로 기대한다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.1
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• pp.17-24
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• 2014

In this paper, we implement and evaluate the performance of a vector-based rasterization algorithm for 3D graphics by using a SIMD (single instruction multiple data) many-core processor architecture. In addition, we evaluate the impact of a data-per-processing elements (DPE) ratio that is defined as the amount of data directly mapped to each processing element (PE) within many-core in terms of performance, energy efficiency, and area efficiency. For the experiment, we utilize seven different PE configurations by varying the DPE ratio (or the number PEs), which are implemented in the same 130 nm CMOS technology with a 500 MHz clock frequency. Experimental results indicate that the optimal PE configuration is achieved as the DPE ratio is in the range from 16,384 to 256 (or the number of PEs is in the range from 16 and 1,024), which meets the requirements of mobile devices in terms of the optimal performance and efficiency.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.143-146
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• 2003

최근 디지털 당송과 이동통신 단말기의 대중화가 이루어짐에 따라 고화질 고해상도의 멀티미디어 컨텐츠의 이동통신 단말기에서의 재생 서비스에 대한 수요가 증가하고 있다 이동통신 단말기에서 멀티미디어 컨텐츠 재생 서비스를 제공하기 위해서는 디지털 방송 컨텐츠를 단말기에 적합한 컨텐츠로 변환할 필요가 있다. 본 논문은 디지털 방송 규격인 MPEG-2 컨텐츠를 이동통신 단말기에서 지원하는 MPEG-4 SP(Simple Profile) 컨텐츠로 실시간으로 변환하는 트랜스 코더에 대한 설계와 구현 기술을 제안한다. 구현된 트래스코더는 화질 유지와 계산량 감소를 위한 적응적 움직임벡터 재구성, 매크로블록 모드 선택, 그리고 움직임벡터 scaling 등의 알고리즘을 포함하고, 인텔사에서 제공하는 SIMD(Single Instruction Multiple Data) 명령어를 이용하여 최적화되었다. 트랜스코더는 30fps, 8Mbps, $720\times480$ 해상도의 멀티미디어 컨텐츠를 다양한 비트율의 30fps, $352\times240$ 해상도의 MPEG-4 컨텐츠로 실시간 변환할 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.2043-2052
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• 1994

This paper proposes a new parallel ASIC architecture for real-time image processing to reduce inter-processing element (inter-PE) communication overhead, called a Sliding Memory Plane (SliM) Image Processor. The Slim Image Processor consists of $3\times3$ processing elements (PEs) connected by a mesh topology. With easy scalability due to the topology. a set of SliM Image Processors can form a mesh-connected SIMD parallel architecture. called the SliM Array Processor. The idea of sliding means that all pixels are slided into all neighboring PEs without interrupting PEs and without a coprocessor or a DMA controller. Since the inter-PE communication and computation occur simultaneously. the inter-PE communication overhead, significant disadvantage of existing machines greatly diminishes. Two I/O planes provide a buffering capability and reduce the date I/O overhead. In addition, using the by-passing path provides eight-way connectivity even with four links. with these salient features. SliM shows a significant performance improvement. This paper presents architectures of a PE and the SliM Image Processor, and describes the design of an instruction set.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.5
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• pp.471-479
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• 2009

In this paper, we proposed an improved ray tracing method with an amelioration of visible tree structure, a visible face determination method, and non-uniform random test point method. In a proposed visible tree structure, it reduces tree nodes by means of merging similar nodes. In a visible face determination method, it shows that a ray hit test with a packet ray method can reduce a test time. A ray tracing method involving with a packet ray hit test method can improve a tree construction time up to 3.3 times than a ray tracing method with a single ray hit test method. Furthermore, by seeding a non-uniform and random test point on a face, tree construction time is improved up to 1.11 times. Received powers from the proposed ray tracing results and measured results have good agreement with 1.9 dB RMS error.

• Journal of the Korea Society of Computer and Information
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• v.19 no.10
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• pp.1-12
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• 2014

This paper implements and improves the performance of high computational subtractive clustering algorithm using a single instruction, multiple data (SIMD) based many-core processor. In addition, this paper implements five different processing element (PE) architectures (PEs=16, 64, 256, 1,024, 4,096) to select an optimal PE architecture for the subtractive clustering algorithm by estimating execution time and energy efficiency. Experimental results using two different medical images and three different resolutions ($128{\times}128$, $256{\times}256$, $512{\times}512$) show that PEs=4,096 achieves the highest performance and energy efficiency for all the cases.

• Journal of Multimedia Information System
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• v.5 no.3
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• pp.201-208
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• 2018

High Efficiency Video Coding range extensions (HEVC RExt) is a kind of extension model of HEVC. HEVC RExt was specially designed for dealing the high quality images. HEVC RExt is very essential for studio editing which handle the very high quality and various type of images. There are some problems to dealing these massive data in studio editing. One of the most important procedure is re-encoding and decoding procedure during the editing. Various codecs are widely used for studio data editing. But most of the codecs have common problems to dealing the massive data in studio editing. First, the re-encoding and decoding processes are frequently occurred during the studio data editing and it brings enormous time-consuming and video quality loss. This paper, we suggest new video coding structure for the efficient studio video editing. The coding structure which is called "ultra-low delay (ULD)". It has the very simple and low-delayed referencing structure. To simplify the referencing structure, we can minimize the number of the frames which need decoding and re-encoding process. It also prevents the quality degradation caused by the frequent re-encoding. Various fast coding algorithms are also proposed for efficient editing such as tool-level optimization, multi-serve based distributed coding and SIMD (Single instruction, multiple data) based parallel processing. It can reduce the enormous computational complexity during the editing procedure. The proposed method shows 9500 times faster coding speed with negligible loss of quality. The proposed method also shows better coding gain compare to "intra only" structure. We can confirm that the proposed method can solve the existing problems of the studio video editing efficiently.