• Journal of Power Electronics
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• 제16권4호
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• pp.1504-1512
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• 2016

This paper presents a new single-phase asymmetrical cascaded multilevel DC-link inverter. The proposed inverter comprises two stages. The main stage of the inverter consists of multiple similar cells, each of which is a half-bridge inverter consisting of two switches and a single DC source. All cells are connected in a cascaded manner with a fixed neutral point. The DC source values are not made equal to increase the performance of the inverter. The second circuit is a folded cascaded H-bridge circuit operating at a line frequency. One of the main advantages of this proposed topology is that it is a modular type and can thus be extended to high stages without changing the configuration of the main stage circuit. Two control schemes, namely, low switching with selective harmonic elimination and sinusoidal pulse width modulation, are employed to validate the proposed topology. The detailed approach of each control scheme and switching pulses are discussed in detail. A 150W prototype of the proposed system is implemented in the laboratory to verify the validity of the proposed topology.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 학술대회 논문집 전문대학교육위원
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• pp.21-25
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• 1999

This paper proposes a novel control strategy of SVC(Static var compensator) using cascade multilevel inverter. To control the reactive power instantaneously, the dq-dynamic system model is described and analyzed. A single pulse pattern based on the SHE(Selective Harmonic Elimination) technique is determined from the look-up table to reduce the line current harmonics and a rotating fundamental frequency switching scheme is applied to adjust the DC capacitor voltage at the scheme level. From the simulation, it is verified that this proposed control scheme make the dynamic control response of SVC fast, the current harmonics low, and the DC capacitor voltage balanced.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1989년도 추계학술대회 논문집 학회본부
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• pp.296-300
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• 1989

The paper proposes a method to eliminate harmonics of PWM inverter fed induction motor system using Walsh series. In other words, this paper presents technique of the selective harmonics elimination(SHE) by W-FT series in three phase PWM inverter output waveform. A microprocessor(8086 CPU) - controlled three phase induction motor system in order to verify this algorithm is present. It is designed for a three output voltage in the 1$\sim$60 Hz inverter with the 5th and 7th harmonics, 5th, 7th, 11th, and 13th, harmonics eliminated, and with the fundamental wave amplitude proportional to the output frequency. In the PWM inverter, dead time circuit is inserted in the switching si gnats to prevent the de link shortage. This paper is deals with quantative prediction of dead-time effect and its compensation in PWM inverters. The performance of the compensation circuits is confirmed by the experiment.

• 전기학회논문지
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• 제63권8호
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• pp.1046-1054
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• 2014

In this paper, a hardware prototype for the 10kVA 11-level MMC was built and various experimental works were conducted to verify the operation algorithms of MMC. The hardware prototype was designed using computer simulation with PSCAD/EMTDC software. After manufactured in the lab, the hardware prototype was tested to verify the modulation algorithms to form the output voltage, the balancing algorithm to equalize the sub-module capacitor voltage, and the redundancy operation algorithm to improve the system reliability. The developed hardware prototype can be utilized for analyzing the basic operation and performance improvement of MMC according to the modulation and redundancy operation scheme. It also can be utilize to analyze the basic operational characteristics of HVDC system based on MMC.