• Proceedings of the Korea Information Processing Society Conference
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• 2017.11a
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• pp.360-362
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• 2017

올해 초, 구글(Google)이 SHA-1의 충돌 현상을 입증했다. 이것은 모든 타 암호 알고리즘 역시 안전할 수 없다는 것을 뜻하며, 향후 SHA-256을 사용하는 비트코인도 취약해질 수 있음을 의미한다. 이유인즉슨, 비트코인에서 사용되는 암호 및 해시 알고리즘은 답을 찾기 위해 상당한 시간이 소요되지만, 양자 컴퓨터의 큐비트를 바탕으로 하는 연산처리 능력은 그 시간을 대폭 감소시킬 수 있기 때문이다. 본 논문에서는 이와 같은 양자 컴퓨터가 비트코인에 얼마나 위협적일 수 있는지와 더불어 양자 컴퓨터 출현에 대비하고자 등장한 새로운 암호 화폐인 Byteball 및 QRL코인을 살펴보고자 한다.

• Journal of Information Processing Systems
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• v.8 no.1
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• pp.119-132
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• 2012

Recently, a fast and secure hash function SFHA - 256 has been proposed and claimed as more secure and as having a better performance than the SHA - 256. In this paper an improved version of SFHA - 256 is proposed and analyzed using two parameters, namely the avalanche effect and uniform deviation. The experimental results and further analysis ensures the performance of the newly proposed and improved SFHA-256. From the analysis it can be concluded that the newly proposed algorithm is more secure, efficient, and practical.

• Proceedings of the Korean Society of Computer Information Conference
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• 2019.07a
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• pp.359-360
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• 2019

This paper proposes partial sharing and trading of digital content as a method of sharing blockchain idurium-based digital content. The platform has three characteristics and aims to improve the existing digital content sales platform. First, it increases the efficiency of sharing and trading through partial sharing and trading systems of digital content. Second, it will be built in the form of blockchain idurium-based smart contracts to ensure the accuracy of transactions. Third, it is possible to analyze the form factor of the comments by improving the grading system.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.1474-1477
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• 2009

본 논문에서는 ASR(Arithmetic Shift Register)과 SHA-2로 구성된 32비트 출력의 새로운 스트림 암호 ASC를 제안한다. ASC는 소프트웨어 및 하드웨어 구현이 쉽게 디자인된 스트림 암호 알고리즘이다. 특히 계산능력이 제한된 무선 통신장비에서 빠르게 수행할 수 있도록 개발되었다. ASC는 다양한 길이(8-32바이트)의 키를 지원하고 있으며, 워드 단위로 연산을 수행한다. ASC는 매우 간결한 구조를 가지고 있으며 선형 궤환 순서기(Linear Feedback Sequencer)로 ASR을 적용하였고, 비선형 순서기(Nonlinear sequencer)로 SHA-2를 적용하여 크게 두 부분으로 구성되어 있는 결합 함수(combining function) 스트림 암호이다. 그리고 8비트, 16비트, 32비트 프로세스에서 쉽게 구현이 가능하다. 제안한 스트림 암호 ASC는 최근에 표준 블록 암호로 제정된 AES, ARIA, SEED등의 블록 암호보다는 6-13배 빠른 결과를 보여주고 있으며, 안전성 또한 현대 암호 알고리즘이 필요로 하는 안전성을 만족하고 있다.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.204-206
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• 2011

기존의 TAR와 같은 아카이브 포맷은 파일의 중복을 제거하는 기능이 포함되지 않아 리눅스 배포 미러와 같이 버전단위로 저장되는 시스템에서 디스크 공간의 낭비가 발생했다. 본 연구에서는 중복 제거 기능이 포함된 아카이브 포맷인 DTAR와 이를 지원하는 DTM 유틸리티를 제안하였다. 주요 아이디어는 DTAR 헤더에 SHA1 해시를 삽입하고 SHA1 해시를 노드로 하는 R-B Tree를 생성하여 중복을 검색 및 제거하는 것이다. 실험 결과 DTAR가 tar.gz보다 최대 31% 공간을 절약하고, 수행 시간도 줄어드는 것을 확인하여 효율적임을 보였다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.1
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• pp.31-39
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• 2016

Hash function is a cryptographic primitive which conduct authentication, signature and data integrity. Recently, Wang et al. found collision of standard hash function such as MD5, SHA-1. For that reason, National Security Research Institute in Korea suggests a secure structure and efficient hash function, LSH. LSH consists of three steps, initialization, compression, finalization and computes hash value using addition in modulo $2^W$, bit-wise substitution, word-wise substitution and bit-wise XOR. These operation is parallelizable because each step is independently conducted at the same time. In this paper, we analyse LSH structure and implement it over SIMD-SSE, AVX and demonstrate the superiority of LSH.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.143-146
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• 2011

A 50-MS/s 10-bit pipelined ADC with 1.2Vpp differential input range is proposed in this paper. The designed pipelined ADC consists of eight stage of 1.5bit/stage, one stage of 2bit/stage, digital error correction block, bias & reference driver, and clock generator. 1.5bit/stage is consists of sub-ADC, DAC and gain stage, Specially, a sample-and hold amplifier (SHA) is removed in the designed pipelined ADC to reduce the hardware and power consumption. Also, the proposed bootstrapped switch improves the Linearity of the input analog switch and the dynamic performance of the total ADC. The reference voltage was driven by using the on-chip reference driver without external reference. The proposed pipelined ADC was designed by using a 0.18um 1-poly 5-metal CMOS process with 1.8V supply. The total area including the power decoupling capacitor and power consumption are $0.95mm^2$ and 60mW, respectively. Also, the simulation result shows the ENOB of 9.3-bit at the Nyquist sampling rate.

• Health Policy and Management
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• v.13 no.4
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• pp.48-65
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• 2003

Detailed analyses of total health expenditure and its sub­categories are essential for the evidence­based health policy(EBHP). These analyses, again, should be based on timely and reliable data that are comparable across countries. The System of Health Accounts (SHA), published by the OECD in 2000, provides an integrated system of comprehensive and internationally comparable accounts. The author has implemented the SHA manual into Korean situation, and examined overall expenditure estimate and its basic functional breakdown following the manual. This study explains how pharmaceutical expenditure is estimated. The results are, then, analyzed particularly from the international perspective. Both administrative data in Statistical Yearbooks (National Health Insurance, Medical Aid, Industrial Accident Compensation Insurance) and survey data on Health and Nutrition are used for the estimation. Per capita pharmaceutical expenditure in Korea (183 US$ PPPs) was far less than the OECD average (308 US$ PPPs) in 2001, but pharmaceutical expenditure share in total health expenditure (20.3％) was higher than the average (16.7％). This can be explained by the fact that there is a statistically significant correlation between pharmaceutical expenditure share and per capita GDP of each country. Korean people follow the tendency of relatively low­income countries to spend less than OECD average for health care, but follow again their tendency to spend more on drugs than on other health care services. In consideration of results and analysis as above, per capita pharmaceutical expenditure in Korea is expected to grow in the future, but the growth rate of the pharmaceutical expenditure is expected to be less than that of overall health expenditure.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.2
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• pp.1-12
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• 2013

Information Security System is implemented in software, hardware and FPGA device. Implementation of S/W provides high flexibility about various information security algorithm, but it has very vulnerable aspect of speed, power, safety, and performing ASIC is really excellent aspect of speed and power but don't support various security platform because of feature's realization. To improve conflict of these problems, implementation of recent FPGA device is really performed. The goal of this thesis is to design and develop a FPGA hardware accelerator for information security system. It performs as AES, SHA-256 and ECC and is controlled by the Integrated Interface. Furthermore, since the proposed Security Information System can satisfy various requirements and some constraints, it can be applied to numerous information security applications from low-cost applications and high-speed communication systems.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.98-107
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• 2013

This work describes a 13b 100 MS/s 0.13 um CMOS four-stage pipeline ADC for 3G communication systems. The proposed SHA-free ADC employs a range-scaling technique based on switched-capacitor circuits to properly handle a wide input range of $2V_{P-P}$ using a single on-chip reference of $1V_{P-P}$. The proposed range scaling makes the reference buffers keep a sufficient voltage headroom and doubles the offset tolerance of a latched comparator in the flash ADC1 with a doubled input range. A two-step reference selection technique in the back-end 5b flash ADC reduces both power dissipation and chip area by 50%. The prototype ADC in a 0.13 um CMOS demonstrates the measured differential and integral nonlinearities within 0.57 LSB and 0.99 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 64.6 dB and a maximum spurious-free dynamic range of 74.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.2 $mm^2$ consumes 145.6 mW including high-speed reference buffers and 91 mW excluding buffers at 100 MS/s and a 1.3 V supply voltage.