• Proceedings of the Korea Society for Industrial Systems Conference
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• 2000.05a
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• pp.125-134
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• 2000

In this paper, we proposed a new circuit construction method that reduced the number of CMOS devices of singleton fuzzy controller(SFC) through the proposing a new membership function circuit(MFC) which uses the language variable selecting and the coefficient selecting circuit. According to the range of input values, we can choose the language variables beforehand which will be used in the inference. So we proposed the new MFC which generates the only necessary language variables. Also, we removed all rules of which adapting degree of their antecedents is zero through proposing the coefficient selecting circuit which beforehand selects the coefficients which will influence the inference result. Though this method, we simplified the structure of SFC and reduced the size of hardware. And to solve the problem in the current mode with respect to the restriction of the fan-out number, voltage-input and current-out membership function circuits are constituted of operational transconductance amplifiers. A membership function circuit which includes the language variable selecting circuit, a minimum operation circuit we implemented by current mode CMOS devices. As a result of applying proposed method, total numbers of blocks and devices wave decreased. If the number of variables and antecedents are getting larger, this method is more efficient.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2000.11a
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• pp.357-365
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• 2000

In this paper, we proposed a new circuit construction method that reduced the number of CMOS devices of singleton fuzzy controller(SFC) through the proposing a new membership function circuit(MFC) which uses the language variable selecting and the coefficient selecting circuit. According to the range of input values, we can choose the language variables beforehand which will be used in the inference. So we proposed the new MFC which generates the only necessary language variables. Also, we removed all rules of which adapting degree of their antecedents is zero through proposing the coefficient selecting circuit which beforehand selects the coefficients which will influence the inference result. Though this method, we simplified the structure of SFC and reduced the size of hardware. And to solve the problem in the current mode with respect to the restriction of the fan-out number, voltage-input and current-out membership function circuits are constituted of operational transconductance amplifiers. A membership function circuit which includes the language variable selecting circuit, a minimum operation circuit we implemented by current mode CMOS devices. As a result of applying proposed method, total numbers of blocks and devices wave decreased. If the number of variables and antecedents are getting larger, this method is more efficient.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.04a
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• pp.171-176
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• 2001

This paper describes the methodology of an IEC 1131-3-based control logic generator for the control system design and converting algorithm between programmable languages. The proposed control logic generator is generated based on the software model and common element with data type, variables, POUs(program organization unit) and execution control unit commonly used within programmable languages of IEC 1131-3 Standard. The generation method of object file was proposed on five programmable language based on IECI 131-3. The generation method of object file is represented as following; 1) the generation method using conversion algorithm from LD to IL with FBD(function block diagram), 2) the generation method using C code generation algorithm from SFC using the SFC execution sequence with FBD and ST(structured text). The proposed control logic generator was implemented by Visual C++ and MFC on MS-windows NT 4.0

• Journal of Korean Institute of Industrial Engineers
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• v.25 no.2
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• pp.150-161
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• 1999

This paper deals with the design and development of a real-time integrated communication architecture for heterarchical SFCS(Shop Floor Control System). In autonomous agent-based heterarchical SFCS, each functional unit of parts and resources is equipped with an intelligent controller (agent) that acts as the representative of the entity. The controllers communicate and negotiate with other controllers on a real-time basis through message passing and bidding protocol to achieve mutual agreements for task sharing. ICPL(Integrated Communication Protocol and Language) is proposed for this purpose. ICPL is a language and a protocol for supporting communication among intelligent controllers. Based on the speech act theory, this paper proposes a semantic description for ICPL that associates the description of the cognitive states of controllers with the use of language primitives (message_type). Semantics for the basic set of ICPL messages is described. Eventually, an ICPL-based communication architecture can provide the implementation of the distributed and heterarchical SFCS, and makes the intelligent controller transparent to the negotiation problem.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.1012-1017
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• 1993

In this paper, the instruction set and the architecture of a RISC processor for programmable logic controller is suggested. From the measurement of existing programs, the characteristics of ladder instructions are analyzed. The instruction set is defined so that the existing ladder program can be reused with simple translation. Because bit instructions controls the behavior of word instructions, the processor suits for high level language like SFC. Simulations show that the PLC with the suggested processor is twenty times faster than the PLC with the multi-purpose microprocessor.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.305-307
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• 2009

When we design the control system used Programmable Logic Controller(PLC), we program the main algorithm by Ladder Diagram(LD) among the standard language. We can substitute the select sequence function by the unique sequence. We can implement this function by the delay time. Therefore this thesis show the select sequence function by the unique sequence and we confirmed its feasibility through actual example.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1013-1016
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• 2002

제어 시스템에 사용되는 흐름 제어 언어로는 IL(Instruction List), ST(Structured Text), FBD(Function Block Diagram), SFC(Sequential Function Chart), LD (Ladder Diagram)가 있다. 일반적으로 제어 시스템에 탑재하여 사용하는 언어는 상기 언어 중 두 종류 이하의 특정 언어로 제한되어 있다. 이러한 제약을 보완하기 위해, 모든 흐름 제어 언어를 통합 분석할 수 있는 통합 분석기가 필요하다. 본 논문에서는 흐름 제어 언어의 통합 분석 처리가 가능하도록 그래픽 표현의 FBD 를 문자 표현의 EST(Extended Structured Text)로 변형하는 규칙과 문자 표현의 EST 를 IL 로 변형하는 규칙을 제시한다. 언어간의 변형 과정에서 FBD 를 ST 로 표현할 수 없는 부분을 EST 로 정의한다. 또한 본 논문에서 제안된 EST 를 기반으로 통합 분석기의 구조를 제시한다.