• Title/Summary/Keyword: Resistance-capacitance

Search Result 459, Processing Time 0.025 seconds

Circuit Extraction from MOS/LSI Mask Layout (집적회로 마스크 도면으로부터의 회로 추출)

  • Kim, Sung Soo;Kyung, Chong Min
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.23 no.6
    • /
    • pp.981-987
    • /
    • 1986
  • This paper describes the CIREX(CIRcuit EXtractor), an automated CMOS circuit extraction program which provides SPICE2 input file by computing circuit connectivity and transistor dimensions from the CIF file. The CIREX also computes parasitic capacitance and resistance which makes it a valuable tool for timing analysis and detailed circuit simulation. A lattice model is used to calculate the interconnection resistances and substrate capacitances which can be replaced, as an option, by a node model for the worst case timing analysis of the circuit.

  • PDF

Grain Boundary Trap Levels in ZnO-based Varistor (ZnO계 바리스터의 입계포획준위)

  • Kim, Myung-Chul;Park, Soon-Ja
    • Korean Journal of Materials Research
    • /
    • v.2 no.1
    • /
    • pp.12-18
    • /
    • 1992
  • The trap levels of ZnO-based varistor are obtained by Isothermal Capacitance Transient Spectroscopy method. Here ICTS measuring system consists of YHP 4192A Impedance Analyzer and a personal computer for the data acquisition. Between $-40^{\circ}C$ and $60^{\circ}C$, the grain boundary trap levels of 0.48 and 0.94eV were detected for $ZnO-Bi_2O_3-MnO$ system. The hole omission spectra are observed in the case of the addition of CoO into the $ZnO-Bi_2O_3$ system, while the electron emission spectra are detected in the case of the addition of MnO. The nonlinear resistance coefficient $\alpha$ increases with the decrease of the dormer concentration. Finally, the trap level density of $ZnO-Bi_2O_3-MnO$ system is found to decrease with the amount of CoO, while $\alpha$ is found to increase with the amount of CoO.

  • PDF

A New High-Efficiency CMOS Darlington-Pair Type Bridge Rectifier for Driving RFID Tag Chips (RFID 태그 칩 구동을 위한 새로운 고효율 CMOS 달링턴쌍형 브리지 정류기)

  • Park, Kwang-Min
    • Journal of the Korea Academia-Industrial cooperation Society
    • /
    • v.13 no.4
    • /
    • pp.1789-1796
    • /
    • 2012
  • In this paper, a new high-efficiency CMOS bridge rectifier for driving RFID tag chips is designed and analyzed. The input stage of the proposed rectifier is designed as a cascade structure connected with two NMOSs for reducing the gate capacitance by circuitry method, which is the main path of the leakage current that is increased when the operating frequency is increased. This gate capacitance reduction technique using the cascade input stage for reducing the gate leakage current is presented theoretically. The output characteristics of the proposed rectifier are derived analytically using its high frequency small-signal equivalent circuit. For the general load resistance of $50K{\Omega}$, the proposed rectifier shows better power conversion efficiencies of 28.9% for 915MHz UHF (for ISO 18000 -6) and 15.3% for 2.45GHz microwave (for ISO 18000-4) than those of 26.3% and 26.8% for 915MHz, and 13.2% and 12.6% for 2.45GHz of compared other two existing rectifiers. Therefore, the proposed rectifier may be used as a general purpose rectifier to drive tag chips for various RFID systems.

A Study on the Device Characteristics of NMOSFETs Having Elevated Source/drain Made by Selective Epitaxial Growth(SEG) of Silicon (실리콘 선택적 결정 성장 공정을 이용한 Elevated Source/drain물 갖는 NMOSFETs 소자의 특성 연구)

  • Kim, Yeong-Sin;Lee, Gi-Am;Park, Jeong-Ho
    • The Transactions of the Korean Institute of Electrical Engineers C
    • /
    • v.51 no.3
    • /
    • pp.134-140
    • /
    • 2002
  • Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.

Analysis of $f_T$ and $f_{max}$ Dependence on Unit Gate Finger Width for RF Performance Optimization of MOSFETs (MOSFET의 RF 성능 최적화를 위한 단위 게이트 Finger 폭에 대한 $f_T$$f_{max}$의 종속데이터 분석)

  • Cha, Ji-Yong;Cha, Jun-Young;Jung, Dae-Hyoun;Lee, Seong-Hearn
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.45 no.9
    • /
    • pp.21-25
    • /
    • 2008
  • In this study, to maximize RF performance of MOSFETs, $f_T$ and $f_{max}$ dependent data on $W_u$ are measured and newly analyzed by extracting small-signal model parameters. From the physical analysis results, it is found that a peak value of $f_T$ is generated by $W_u$-independent parasitic gate-bulk capacitance at narrow $W_u$ and the wide width effect of reducing the increasing rate of transconductance at wide $W_u$. In addition, it is revealed that a maximum value of $f_{max}$ is caused by the non-quasi-static effect that the gate resistance is greatly reduced at narrow $W_u$ and becomes constant at wide $W_u$.

Electrochemical Characteristics of Hybrid Capacitor and Pulse Performance of Hybrid Capacitor / Li-ion Battery (Hybrid Capacitor의 전기화학적 특성 및 Hybrid Capacitor / Li-ion Battery의 펄스 방전 특성)

  • Lee, Sun-Young;Kim, Ick-Jun;Moon, Seong-In;Kim, Hyun-Soo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.18 no.12
    • /
    • pp.1133-1138
    • /
    • 2005
  • In this study, we have prepared, as the pluse power source, a commercially supplied Li-ion battery with a capacity of 700 mAh and AC resistivity of 60 md at 1 kHz and nonaqeous asymmetric hybrid capacitor composed of an activated carbon cathode and MCMB anode, and have examined the electrochemical characteristics of hybrid capacitor and the pulse performances of parallel connected hybrid capacitor/Li-ion battery source. The nonaqueous asymmetric hybrid capacitors constituted with each stack number of pairs composed of the cathode, the porous separator and the anode electrode were housed in Al-laminated film cell. The 10 stacked hybrid capacitor, which was charged and discharged at a constant current at 0.25 $mA/cm^2$ between 3 and 4.3 V, has exhibited the capacitance of 108F and the lowest equivalent series resistance was 32 $m{\Omega}$ at 1 kHz. On the other hand, the enhanced run time of Li-ion battery assisted by the hybrid capacitor was obtained with increasing of current density and pulse width in Pulse mode. The best improvement, $84\;\%$ for hybrid capacitor/Li-ion battery was obtained in the condition of a 7C-rate pulse (100 msec)/0.5C-rate standby/$10\;\%$ duty cycle.

Design and Analysis of a NMOS Gate Cross-connected Current-mirror Type Bridge Rectifier for UHF RFID Applications (UHF RFID 응용을 위한 NMOS 게이트 교차연결 전류미러형 브리지 정류기의 설계 및 해석)

  • Park, Kwang-Min
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.45 no.6
    • /
    • pp.10-15
    • /
    • 2008
  • In this paper, a new NMOS gate cross-connected current-mirror type bridge rectifier for UHF RFID applications is presented. The DC converting characteristics of the proposed rectifier are analyzed with the high frequency equivalent circuit and the gate capacitance reduction technique for reducing the gate leakage current due to the increasing of operating frequency is also proposed theoretically by circuitry method. As the results, the proposed rectifier shows nearly same DC output voltages as the existing NMOS gate cross-connected rectifier, but it shows the gate leakage current reduced to less than 1/4 and the power consumption reduced more than 30% at the load resistor, and it shows more stable DC supply voltages for the valiance of load resistance. In addition, the proposed rectifier shows high enough and well-rectified DC voltages for the frequency range of 13.56MHz HF(for ISO 18000-3), 915MHz UHF(for ISO 18000-6), and 2.45 GHz microwave(for ISO 18000-4). Therefore, the proposed rectifier can be used as a general purpose one to drive RFID transponder chips on various RFID systems which use specified frequencies.

Electrical and Mechanical Properties of Cu(Mg) Film for ULSI Interconnect (고집적 반도체 배선용 Cu(Mg) 박막의 전기적, 기계적 특성 평가)

  • 안재수;안정욱;주영창;이제훈
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.10 no.3
    • /
    • pp.89-98
    • /
    • 2003
  • The electrical and mechanical properties of sputtered Cu(Mg) films are investigated for highly reliable interconnects. The roughness, adhesion, hardness and resistance to thermal stress of Cu(Mg) film annealed in vacuum at $400^{\circ}C$ for 30min were improved than those of pure Cu film. Moreover, the flat band voltage(V$_{F}$ ) shift in the Capacitance-Voltage(C-V) curve upon bias temperature stressing(BTS) was not observed and leakage currents of Cu(Mg) into $SiO_2$ were three times less than those of pure Cu. Because Mg was easy to react with oxide than Cu and Si after annealing, the Mg Oxide which formed at surface and interface served as a passivation layer as well.

  • PDF

Evaluation and Comparison of Nanocomposite Gate Insulator for Flexible Thin Film Transistor

  • Kim, Jin-Su;Jo, Seong-Won;Kim, Do-Il;Hwang, Byeong-Ung;Lee, Nae-Eung
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2014.02a
    • /
    • pp.278.1-278.1
    • /
    • 2014
  • Organic materials have been explored as the gate dielectric layers in thin film transistors (TFTs) of backplane devices for flexible display because of their inherent mechanical flexibility. However, those materials possess some disadvantages like low dielectric constant and thermal resistance, which might lead to high power consumption and instability. On the other hand, inorganic gate dielectrics show high dielectric constant despite their brittle property. In order to maintain advantages of both materials, it is essential to develop the alternative materials. In this work, we manufactured nanocomposite gate dielectrics composed of organic material and inorganic nanoparticle and integrated them into organic TFTs. For synthesis of nanocomposite gate dielectrics, polyimide (PI) was explored as the organic materials due to its superior thermal stability. Candidate nanoprticles (NPs) of halfnium oxide, titanium oxide and aluminium oxide were considered. In order to realize NP concentration dependent electrical characteristics, furthermore, we have synthesized the different types of nanocomposite gate dielectrics with varying ratio of each inorganic NPs. To analyze gate dielectric properties like the capacitance, metal-Insulator-metal (MIM) structures were prepared together with organic TFTs. The output and transfer characteristics of organic TFTs were monitored by using the semiconductor parameter analyzer (HP4145B), and capacitance and leakage current of MIM structures were measured by the LCR meter (B1500, Agilent). Effects of mechanical cyclic bending of 200,000 times and thermally heating at $400^{\circ}C$ for 1 hour were investigated to analyze mechanical and thermal stability of nanocomposite gate dielectrics. The results will be discussed in detail.

  • PDF

Synthesis and Electrochemical Characteristics of Spherical Li4Ti5O12/CNT Composite Materials for Hybrid Capacitors

  • Yang, Joeng-Jin;Kim, Yu-Ri;Jeong, Moon-Gook;Yuk, Yong-Jae;Kim, Han-Joo;Park, Soo-Gil
    • Journal of Electrochemical Science and Technology
    • /
    • v.6 no.2
    • /
    • pp.59-64
    • /
    • 2015
  • Spherical Li4Ti5O12 and Li4Ti5O12 carbon nanotube (CNT) composites were synthesized using a colloid system. The electrochemical properties of the composites were thoroughly examined to determine their applicability as hybrid capacitor anodes. The electrical conductivity of the spherical Li4Ti5O12-CNT composite was improved over that of the spherical Li4Ti5O12 composite. The synthesized composites were utilized as the anode of a hybrid capacitor, which was assembled with an activated carbon (AC) positive electrode. The CNTs attached on the spherical Li4Ti5O12 particles contributed to a 51% reduction of the equivalent series of resistance of the Li4Ti5O12-CNTs/AC hybrid capacitor compared to the Li4Ti5O12/AC hybrid capacitor. Moreover, the Li4Ti5O12-CNTs/AC hybrid capacitor showed a larger capacitance than the Li4Ti5O12/AC hybrid capacitor; specifically, the Li4Ti5O12-CNT/AC hybrid capacitor showed 1.6 times greater capacitance at 40 cycles with a 10 mA cm−2 loading current density.