• Journal of IKEEE
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• v.22 no.4
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• pp.896-900
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• 2018

Traditionally, Linear Shift Feedback Register (LFSR) has been widely employed to implement Cyclic Redundant Check (CRC) codes for a serial input. Since many applications including network and storage systems demand as high throughput as ever, various efforts have been made to implement CRC hardware to support parallel inputs. Among various parallel schemes, the look-ahead scheme is one of the most widely used schemes due to its short critical path. However, it is very cumbersome to design HDL codes for parallel CRC codes since the look-ahead scheme is inevitable to consider how register and input values move in the next cycles. Thus, this paper proposes a novel CRC hardware generator, which automatically produces HDL codes given a CRC polynomial and parallel factor. The experimental results verify the applicability to use the proposed generator by analyzing the synthesis results from the generated HDL code.

• The KIPS Transactions:PartB
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• v.14B no.7
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• pp.493-502
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• 2007

An on-line registration technique is presented to register multi-view range images for the 3D reconstruction of real objects. Using a range camera, we first acquire range images and photometric images continuously. In the range images, we divide object and background regions using a predefined threshold value. For the coarse registration of the range images, the centroid of the images are used. After refining the registration of range images using a projection-based technique, we use a modified KLT(Kanade-Lucas-Tomasi) tracker to match photometric features in the object images. Using the modified KLT tracker, we can track image features fast and accurately. If a range image fails to register, we acquire new range images and try to register them continuously until the registration process resumes. After enough range images are registered, they are integrated into a 3D model in offline step. Experimental results and error analysis show that the proposed method can be used to reconstruct 3D model very fast and accurately.

• Journal of Navigation and Port Research
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• v.41 no.5
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• pp.303-318
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• 2017

In the shipping industry, it is well known that around 80 % or more of all marine accidents are caused fully or at least in part by human error. In this regard, the International Maritime Organization (IMO) stated that the study of human factors would be important for improving maritime safety. Consequently, the IMO adopted the Casualty Investigation Code, including guidelines to assist investigators in the implementation of the Code, to prevent similar accidents occurring again in the future. In this paper, a process of the human factors investigation is proposed to provide investigators with a guide for determining the occurrence sequence of marine accidents, to identify and classify human error-inducing underlying factors, and to develop safety actions that can manage the risk of marine accidents. Also, an application of these investigation procedures to a collision accident is provided as a case study This is done to verify the applicability of the proposed human factors investigation procedures. The proposed human factors investigation process provides a systematic approach and consists of 3 steps: 'Step 1: collect data & determine occurrence sequence' using the SHEL model and the cognitive process model; 'Step 2: identify and classify underlying human factors' using the Maritime-Human Factor Analysis and Classification System (M-HFACS) model; and 'Step 3: develop safety actions,' using the causal chains. The case study shows that the proposed human factors investigation process is capable of identifying the underlying factors and indeveloping safety actions to prevent similar accidents from occurring.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.49-58
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• 2005

In this paper, we proposed a blind watermarking algerian to use characteristics of a scalar quantizer which is the recommended in the JPEG2000 and JPEG. The proposed algorithm shifts a quantization index according to the value of each watermark bit to prevent losing the watermark information during the compression by quantization. Therefore, the watermark is embedded during the process of quantization, not an additional process for watermarking, and is adaptively applied as a assigned quantizer according application areas. Before embedding process, a LFSR(Linear feedback shift register) rearranged the watermark for the security of the watermark itself and in the embedding process, a LFSR is used to hide the watermarking positions. Therefore the embedded watermark can he extracted by only the owner who knows the initial value of LFSR without the original image. The visual recognizable pattern such as a binary image was used as the watermark. The experimental results showed that the proposed algerian satisfies the robustness and imperceptibility corresponding to the major requirement of watermarking. The results showed the largest error rate to be $5.7\%$ for attack. The experimental result which compares the proposed algorithm with the Mohamed algorithm showed that the proposed algorithm was better than it, exactly $4\~5$ times for the attacks of JPEG and JPEG2000.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.9-15
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• 2003

An optimized finite-field multiplier is proposed for encryption and error correction devices. It is based on a modified Linear Feedback Shift Register (LFSR) which has lower power consumption and smaller area than prior LFSR-based finite-field multipliers. The proposed finite field multiplier for GF(2n) multiplies two n-bit polynomials using polynomial basis to produce $z(x)=a(x)^*b(x)$ mod p(x), where p(x) is a irreducible polynomial for the Galois Field. The LFSR based on a serial multiplication structure has less complex circuits than array structures and hybrid structures. It is efficient to use the LFSR structure for systems with limited area and power consumption. The prior finite-field multipliers need 3${\cdot}$m flip-flops for multiplication of m-bit polynomials. Consequently, they need 6${\cdot}$m latches because one flip-flop consists of two latches. The proposed finite-field multiplier requires only 4${\cdot}$m latches for m-bit multiplication, which results in 1/3 smaller area than the prior finite-field multipliers. As a result, it can be used effectively in encryption and error correction devices with low-power consumption and small area.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.1
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• pp.66-75
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• 2002

For the theoretical performance analysis of Viterbi Decoder for wireless LAN with data rate 12Mbps, code rate 1/2 and constraint length 7 defined in IEEE 802.11a, the transfer function is derived using Cramer's rule and the first-event error probability and bit error probability is derived under the AWGN. In the design process, input symbol is quantized into 16 steps for 4 bit soft decision and register exchange method instead of memory method is proposed for trace back, which enables the majority at the final decision stage. In the implementation, the Viterbi decoder based on parallel architecture with pipelined scheme for processing 12Mbps high speed data rate and AWGN generator are implemented using FPGA chips. And then its performance is verified in real time.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.7
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• pp.700-710
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• 2009

A computer vision technique of estimating the location of an unmanned ground vehicle is proposed. Identifying the location of the unmaned vehicle is very important task for automatic navigation of the vehicle. Conventional positioning sensors may fail to work properly in some real situations due to internal and external interferences. Given a DSM(Digital Surface Map), location of the vehicle can be estimated by the registration of the DSM and multiview range images obtained at the vehicle. Registration of the DSM and range images yields the 3D transformation from the coordinates of the range sensor to the reference coordinates of the DSM. To estimate the vehicle position, we first register a range image to the DSM coarsely and then refine the result. For coarse registration, we employ a fast random sample matching method. After the initial position is estimated and refined, all subsequent range images are registered by applying a pair-wise registration technique between range images. To reduce the accumulation error of pair-wise registration, we periodically refine the registration between range images and the DSM. Virtual environment is established to perform several experiments using a virtual vehicle. Range images are created based on the DSM by modeling a real 3D sensor. The vehicle moves along three different path while acquiring range images. Experimental results show that registration error is about under 1.3m in average.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.8-16
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• 1999

This paper describes a VLSI design of Reed-Solomon(RS) decoder using the modified Euclid algorithm, with the main theme focused on the $\textit{GF}(2^8)$. To get area-efficient design, a number of new architectures have been devised with maximal register and Euclidean ALU unit sharing. One ALU is shared to replace 18 ALUs which computes an error locator polynomial and an error evaluation polynomial. Also, 18 registers are shared to replace 24 registers which stores coefficients of those polynomials. The validity and efficiency of the proposed architecture have been verified by simulation and by FLEX$^TM$ FPGA implementation in hardware description language VHDL. The proposed Reed-Solomon decoder, which has the capability of decoding RS(208,192,17) and RS(182,172,11) for Digital Versatile Disc(DVD), has been designed by using O.6$\mu\textrm{m}$ CMOS TLM Compass$^TM$ technology library, which contains totally 17k gates with a core area of 2.299$\times$2.284 (5.25$\textrm{mm}^2$). The chip can run at 20MHz while the DVD requirement is 3.74MHz.

• Journal of Environmental Impact Assessment
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• v.14 no.3
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• pp.97-107
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• 2005

The purpose of this study is to develop a system, which estimates watershed pollutant loading rate through the combination of GIS and computational mode. Also, the applicability of this study was estimated by the application of the above system for Chuncheon City. The detailed results of these studies are as follows; The pollutant loading estimation system was developed for more convenient estimation of pollutant loading rate in watershed, and the system load was minimized by the separation of estimation module for point and non-point source. This system on the basis of GIS is very economical and efficient because it can be applied to other watershed with the watershed map. System modification is not needed. The pollutant loading estimation system for point source was developed to estimate the pollutant loading rate in watershed through the extraction of the proper data from all districts and yearly data and the execution of spatial analysis which is main function of GIS. From the verification result of spatial analysis, real watershed area and the administrative districtarea extracted by spatial analysis were $1,114,893,340.15m^2$ and $1,114,878,683.68m^2$, respectively. It shows that the spatial analysis results were very exact with only 0.001% error. The pollutant loading estimation system for non-point source was developed to calculate the pollutant loading rate through the overlaying of land-use and watershed map after the construction of new land-use map using the land register database with most exact land use classification. Application result for Chuncheon City shows that the proposed system results in one percent land use error while the statistical method results in five percent. More exact nonpoint source pollutant loading was estimated from this system.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.244-249
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• 2010

The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.