• Journal of the Korean Society for Precision Engineering
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• v.31 no.8
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• pp.653-658
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• 2014

Roll-to-Roll printing process has become a great issue as a breakthrough for low cost and mass production of electronic devices such as organic thin film transistor, and etc. To print the electronic devices, multi-layer printing is essential, and high precision register control is required for this process. Unlike stop-and-repeat printing process, it is impossible to control the register in a static state since the roll-to-roll process is a continuous system. Therefore, the behavior of web such as polyethylene terephthalate (PET) and polyimide (PI) by the tensile and thermal stress generated in the roll-to-roll process as well as motor control of driven rolls has to be considered for a high precision register control. In this study, the correlation between curing temperature and thermal deformation of PET web is analyzed. Finally, it is verified experimentally that the temperature disturbance generates the more serious register error under the higher curing temperature.

• Journal of IKEEE
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• v.27 no.4
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• pp.683-686
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• 2023

In this paper, we designed a Delayed Dual Core Lock-Step (D-DCLS) processor where two cores operate same instructions with delay and the result is compared to mitigate soft errors and common mode failures in automotive electronic systems. Because D-DCLS does not know which core an error occurred in, each core must be recovered to the point before the error occurred, but complex hardware modifications are required to return all intermediate values on the pipeline stage. In this paper, in order for easy hardware implementation, all register values are saved to a buffer whenever a branch instruction is executed. When an error is detected, the saved register values are automatically restored, and then 'BX LR' instruction is executed to return to the last branch point. The proposed D-DCLS processor was designed using Verilog HDL and was confirmed to continue normal operation after automatically recovering error.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2007.06a
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• pp.461-462
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• 2007

• International Journal of Internet, Broadcasting and Communication
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• v.12 no.2
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• pp.144-149
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• 2020

A database called Home Location Register(HLR) plays a major role in location management in mobile cellular networks. The objectives of this paper are to identify the problems of the current HLR system through rigorous analysis, to suggest solutions to them. The current HLR backup method is a process of simply writing the changed memory SLD block to disk, which has a problem in maintaining database consistency. Since information change and backup are performed separately by separate processes, there is a risk of information inconsistency when an error restart occurs. To solve this problem, a transaction concept was introduced for subscriber-related operation functions and a recovery method through logging and checkpointing was introduced. The subscriber related functions of tasks terminated normally by the suggested process are recovered with consistency even after system restarts. Performance is also not affected seriously because disk tasks for log occur with only subscriber related functions.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.152-156
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• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• Journal of the Ergonomics Society of Korea
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• v.30 no.1
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• pp.137-150
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• 2011

Nationally and internationally reported statistics on marine accidents show that 80% or more of all marine accidents are caused fully or in part by human error. According to the statistics of marine accident causes from Korean Maritime Safety Tribunal(KMST), operating errors are implicated in 78.7% of all marine accidents that occurred from 2002 to 2006. In the case of the collision accidents, about 95% of all collision accidents are caused by operating errors, and those human error related collision accidents are mostly caused by failure of maintaining proper lookout and breach of the regulations for preventing collision. One way of reducing the probability of occurrence of the human error related marine accidents effectively is by investigating and understanding the role of the human elements in accident causation. In this paper, causal factors/root causes classification systems for marine accident investigation were reviewed and some typical human error analysis methods used in shipping industry were described in detail. This paper also proposed a human error analysis method that contains a cognitive process model, a human error analysis technique(Maritime HFACS) and a marine accident causal chains, and then its application to the actual marine accident was provided as a case study in order to demonstrate the framework of the method.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1007-1010
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• 2005

This paper presents a fingerprint image registration method. In the fingerprint system, the insufficiency of mutual information between a template and a query fingerprint is one of major factors to deteriorate recognition performance. To overcome this problem, we need to register multiple impressions and integrate their information. Our method matches the ridges from multiple impressions recursively and then registers the impressions to minimize the registration error calculated from the Distance map. Our method use regularized TPS model as the transformation model to compensate for the plastic deformation. We compare our method with 3 prior arts (ICP, Distance Map, Ross's method). Our registration error and its' variance is the smallest and also the average registration error is below 3 pixels.

• Proceedings of the KSME Conference
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• 2008.11a
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• pp.1144-1149
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• 2008

Converting technology has developed to print information for the decades. Recently, this technology (like gravure, gravure-offset) is rising as an alternative way for mass production of printed electronics such as RFID, solar cell. For the width of printing line is under 10 microns, registration error should be minimized less than several microns. Tension disturbance is main cause of registration error and this should be minimized before the substrate is transported into printing zone. With PI controller, it is possible to suppress the disturbance within 2% of operating tension. But register error appears more than 10 micron using PIcontroller considering noise. So LQG controller is needed as an alternative control method. In this paper, the comparision of PI and LQG controller in the converting machine including measured noise and tension disturbance is presented. It is shown that the LQG controller is more suitable for precision tension control in printed electronics.

• Proceedings of the KIEE Conference
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• 2006.10d
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• pp.98-100
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• 2006

본 논문은 기존의 고속 인쇄기용 레지스터 컨트롤러가 고가의 외국 제품을 사용해 온 것에 반해 이를 대체 할 뿐 아니라 저렴한 가격의 레지스터 칸트롤러를 개발 하는 것을 목표로 하고 기존 250mpm(meter per minute)의 두 배인 500mpm의 고속 인쇄에서도 사용할 수 있도록 레지스터 컨트롤러를 개발해 오차 보정을 좀 더 정확하고 신속하게 하는 것에 그 목적이 있다.

• The KIPS Transactions:PartC
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• v.10C no.2
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• pp.233-240
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• 2003

In this paper, an improved architecture of turbo codec for IMT-2000 is proposed. The encoder consists of an interleaver using an on-the-fly type address generator and a modified shift register instead of an external RAM, and the decoder uses a decreased number of RAM. The proposed architecture is simulated with C/VHDL languages, where BER (bit-error-rate) performances are generally in agreement with previous data by varying interaction numbers, interleaver block sizes and code rates.