• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.575-578
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• 1998

In this paper, we propose a VLSI architecture of Reed-Solomon decoder. Our goal is the development of an architecture featuring parallel and pipelined processing to improve the speed and low power design. To achieve the this goal, we analyze the RS decoding algorithm to be used parallel and pipelined processing efficiently, and modified the Euclid's algorithm arithmetic part to apply the parallel structure in RS decoder. The overall RS decoder are compared to Shao's, and we show the 10% area efficiency than Shao's time domain decoder and three times faster, in addition, we approve the proposed RS decoders with Altera FPGA Flex 10K-50, and Implemeted with LG 0.6{\mu}$ processing.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2493-2495
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• 2001

Burst Error Channel의 에러 정정 기술로써 Reed-Solomon Product Code(RSPC)가 광범위하게 사용되고 있다. 그러나 Random Error Channel과는 달리 Burst Error Channel 상에서 RSPC의 에러 정정 평가 방법에는 많은 어려움이 있다. 우리는 이번 논문에서 Burst Error Channel 상에서 RSPC의 Error Correction Capability의 확률적인 계산 방법을 기술하려 한다.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3212-3214
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• 1999

RS(Reed-Solomon)부호는 오류 정정을 위한 채널 코딩기법중의 하나로 특히 연집 오류에 대해 강한 특성을 갖고 있으며, CD-P(Compact Disc Player), DAT(Digital Audio Tape). VTR, DVD(Digital Video Disc), 디지탈 TV 디코더등에서 사용되고 있다. 본 논문은 Galois Field, GF[$2^8$]상에서 (204. 188. 8)의 규격을 갖는 디지탈 TV용 RS 복호기의 구현에 관한 연구로 8개의 심볼 오류까지 정정 가능하다. 오증 계산은 16개의 오증 계산셀로 구성되어 지며, 오류 위치 다항식을 계산하는데 있어서는 Berlekamp-Massey 알고리즘을 사용한다. VHDL로 설계되어 Synopsys를 이용하여 검증 및 합성하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.11a
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• pp.250-251
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• 2023

블록체인 원장의 용량이 폭증하면서 여러 확장성 문제들이 나타나고 있다. 이에 대한 해결 방법으로 원장에 Reed-Solomon 부호화를 적용하여 용량을 줄이려는 연구가 일부 진행 중이나, 피어에 장애가 발생하거나 악의적 행동이 있다면, 데이터 손실을 막기 위한 복구 과정이 필수적이다. 본 논문에서는 원장에 Reed-Solomon 부호화를 적용해 얻는 저장 공간의 감소 효과에 비해서 데이터를 복구할 시 어느 정도의 오버헤드가 발생하는지 성능 평가를 수행했다. 결과적으로, 많은 블록 복구가 필요한 상황에서 인코딩/디코딩 시간은 미미하였고, 대부분의 오버헤드는 청크 재전송 시간이었다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.59-67
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• 2013

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

• Information and Communications Magazine
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• v.15 no.11
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• pp.112-123
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• 1998

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.689-692
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• 2008

Hierarchical modulation has been considered for achieving higher data rates in Terrestrial-DMB(T-DMB) systems. And for achieving a higher data rates transmission, the low-priority (LP) data, which is used to carry additional data, such as video data, audio data and textual data, should be perfectly decoded in a certain value of $E_b/N_o$. Unfortunately, the man-made noise badly affects the high-priority (HP) symbol, which is used to carry the conventional data in the existed T-DMB system; and since the advanced T-DMB system is proposed to fit for the legacy T-DMB receivers, the low-priority symbols in the hierarchical modulation are much worse affected by the neighbors, who are both in the same quadrant. Because of the feature that mentioned previously, the turbo code has been considered to deal with the LP data. And due to the degradation which caused by the shortened symbol distance, the error performance of LP data is not sufficient by only using the turbo code. In this paper, we propose a Reed-Solomon code used outside of turbo code, and with the turbo code, it becomes a concatenated code. In this paper, there are some simulation results, within the comparison of those performances, we can see how a Reed-Solomon code is utilized for degradation of error performance which is caused by the hierarchical constellation, and how to design a Reed-Solomon code which is suitable for improving the degradation of error performance.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.3
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• pp.19-26
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• 2017

In this paper, a Linear Error Correction Code, Which is Applicable to Next Generation Wireless Communication System Technology, is Constructed Based on Performance Comparison and Transmission Based on the Premise of High Performance Mobile Rate Enhancement System. This is Because Data Rates are Becoming an Important Issue in Reed-Solomon Codes and Linear Error Code (LDPC) Used in the Physical Layer of Digital Communication and Broadcasting Technologies. Therefore, this paper Simulates the Performance of Reed - Solomon Code and LDPC Applied to Mobile Broadcasting DVB (Digital Video Broadcasting) System and Mobile Broadcasting in Digital Communication and Broadcasting, At this time, Technical Aspects of the Transmission Efficiency and Performance of the LDPC Replacing the Existing Reed-Solomon Code have been Verified from the Viewpoint of Efficiency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1495-1507
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• 1993

In this paper, an implementation of RS (Reed-Solomon) code decoder for CDP (Compact Disc Player) using microprogramming method is presented. In this decoding strategy, the equations composed of Newton's identities are used for computing the coefficients of the error locator polynomial and for checking the number of erasures in C2(outer code). Also, in C2 decoding the values of erasures are computed from syndromes and the results of C1(inner code) decoding. We pulled up the error correctability by correcting 4 erasures or less. The decoder contains an arithmetic logic unit over GF(28) for error correcting and a decoding controller with programming ROM, and also microinstructions. Microinstructions are used for an implementation of a decoding algorithm for RS code. As a result, it can be easily modified for upgrade or other applications by changing the programming ROM only. The decoder is implemented by the Logic Level Modeling of Verilog HDL. In the decoder, each microinstruction has 14 bits( = 1 word), and the size of the programming ROM is 360 words. The number of the maximum clock-cycle for decoding both C1 and C2 is 424.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.38-48
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• 2006

In this paper, we developed a hardware architecture of Reed-Solomon RS(255,239) decoder for the DMB mobile terminals. The DMB provides multimedia broadcasting service to mobile terminals, hence it should have small dimension for low power and short decoding delay for real-time processing. We modified Euclid algorithm to apply it to the key equation solving which is the most complicated part of the RS decoding. We also designed a small finite field divider to avoid the use of large Inverse-ROM table, and it consumed 17 clocks. After synthesis with Synopsis on Samsung STD130 $0.18{\mu}m$ Standard Cell library, the Euclid block had 30,228 gates and consumed 288 clocks, which gave the 25% reduced area compared to other existing designs. The size of the entire RS decoder was about 45,000 gates.