• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1547-1550
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• 2002

Reconfigurable computing is a new computing paradigm which has more potential in terms of performance and flexibility. Reconfigurable computing systems are opening a new era in digital signal processing such as multimedia, communication and consumer electronics because they can filter data rapidly and excel at pattern recognition, image process- ing and encryption. Although many reconfigurable computing systems use a conventional programmable device, they carry several serious problems to be solved. This paper proposes a logic block architecture of programmable device suit-able for the reconfigurable computing. Compared to conventional logic blocks, our logic block can improve implementation density, efficiency and speed.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.2
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• pp.41-46
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• 2015

The demand on low power and high performance system is soaring due to the extending of mobile and small electronic device market. The 3D die-stacking technology is widely studying for next generation integration technology due to its high density and low access time. We proposed the 3D die-stacked DRAM including a reconfigurable accelerator in a logic layer of DRAM. Also we discuss and suggest a cache-based local memory for a reconfigurable accelerator in a logic layer. The reconfigurable accelerator in logic layer of 3D die-stacked DRAM reduces the overhead of data management and transfer due to the characteristics of its location, so that can increase the performance highly. The proposed system archives 24.8 speedup in maximum.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.257-271
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• 2010

As the end of photolithographic integration era is approaching fast, numerous nanoscale devices and systems based on novel nanoscale materials and assembly techniques are recently emerging. Notably, various reconfigurable architectures with considerable promise have been proposed based on nanowire crossbar structure as the primitive building block. Unfortunately, high-density sys-tems consisting of nanometer-scale elements are likely to have numerous physical imperfections and variations. Therefore, defect-tolerance is considered as one of the most exigent challenges in nanowire crossbar systems. In this work, three different defect-avoidant logic mapping algorithms to circumvent defective crosspoints in nanowire reconfigurable crossbar systems are evaluated in terms of various performance metrics. Then, a novel method to find the most cost-effective repair solution is demonstrated by considering all major repair parameters and quantitatively estimating the performance and cost-effectiveness of each algorithm. Extensive parametric simulation results are reported to compare overall repair costs of the repair algorithms under consideration and to validate the cost-driven repair optimization technique.

• Journal of the Optical Society of Korea
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• v.16 no.1
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• pp.13-16
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• 2012

We demonstrate an optical gate architecture using a single SOA to perform AND, OR and NOT logic functions. Simple reconfigurable all-optical logic operations are implemented using RZ modulated signals at 40 Gb/s. Contrast ratio and extinction ratio values have been analysed for the different types of logic gates. Maximum extinction ratio and contrast ratio achieved are 19dB and 17.2 dB respectively. Simple structure and potential for integration makes this architecture an interesting approach in photonic computing and optical signal processing.

• Journal of the Korea Institute of Military Science and Technology
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• v.7 no.3 s.18
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• pp.140-148
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• 2004

Fault detection and isolation(FDI) and reconfigurable flight control system provide better survivability even though actuator faults occur. In this study, a new fault detection and isolation algorithm is proposed using fuzzy logic. When the FDI system detects the actuator fault, the fuzzy logic investigates the state variables to find which actuator has fault. Proposed fuzzy detection algorithm detect not only a single fault but also multiple faults. After detecting the fault, the reconfigurable flight control system begins operating for compensating the effects of the fault. A numerical simulation using six degree-of-freedom nonlinear aircraft model is performed to verity the performance of the proposed fault detection and isolation scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.199-203
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• 2017

Mutually-actuated-nano-electromechanical (MA-NEM) memory switches are proposed for scalability improvement. While conventional NEM memory switches have fixed electrode lines, the proposed MA-NEM memory switches have mutually-actuated cantilever-like electrode lines. Thus, MA-NEM memory switches show smaller deformations of beams in switching. This unique feature of MA-NEM memory switches allows aggressive reduction of the beam length while maintaining nonvolatile property. Also, the scalability of MA-NEM memory switches is confirmed by using finite-element (FE) simulations. MA-NEM memory switches can be promising solutions for reconfigurable logic (RL) circuits.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1187-1188
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• 2008

An area of research called evolvable hardware has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer. In this paper, we have studied and surveyed a gate-level evolvable hardware chip, by integrating both GA hardware and reconfigurable hardware within a single LSI chip. The chip consists of genetic algorithm(GA) hardware, reconfigurable hardware logic, and the control logic. In this paper, we describe the architecture, functions of the chip.

• Proceedings of the Korean Magnestics Society Conference
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• 2017.05a
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• pp.61-62
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• 2017

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.38-49
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• 2006

In this paper, a novel concept based on embedded processor and reconfigurable logic is proposed for efficient manufacturing test and design verification. Unlike traditional gap between design verification and manufacturing test, proposed concept is to combine both design verification and manufacturing test. The semiconductor chip which is using the proposed concept is named "SwToC" and SwToC stands for System with Test On a Chip. SwToC has two main features. First, it has functional verification function on a chip and this function could be made by using embedded processor, reconfigurable logic and memory. Second, it has internal ATE on a chip and this feature also could be made by the same architecture. To evaluate the proposed SwToC, we have implemented SwToC using commercial FPGA device with embedded processor. Experimental results showed that the proposed chip is possible for real application and could have faster verification time than traditional simulation method. Moreover, test could be done using low cost ATE.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.11 no.4
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• pp.305-309
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• 2011

A sparse reconfigurable adaptive filter (SRAF) based on a photonic switch determines the appropriate time delays and weight values for an optical switch implementation of tapped-delay-line (TDL) systems. It is well known that the choice of switch delays is significantly important for efficiently implementing the SRAF. If the same values exist as calculating the sum of weight magnitudes for implementing the connection constraint required by the SRAF, conventional connection algorithm based on sequentially selection the maximum elements might not work perfectly. In an effort to increase the effectiveness of system identification, an upgraded connection algorithm used progressive calculation to obtain the better solution is considered in this paper. The performance of the proposed connection constraint algorithm is illustrated by computer simulation for a system identification application.