• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.58-64
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• 2009

For the success of the reconfigurable computing, the algorithm for mapping operations onto coarse-grained reconfigurable architecture is very important. This paper proposes a resource-aware mapping system for the coarse-grained reconfigurable architecture and its own underlying heuristic algorithm. The operation assignment and the routing path allocation are simultaneously performed with a cycle-accurate time-exclusive resource model. The proposed algorithm minimizes the communication resource usage and the global memory access with the list scheduling heuristic. The operation to be mapped are prioritized with general properties of data flow. The evaluations of the proposed algorithm show that the performance is significantly enhanced in several benchmark applications.

• The KIPS Transactions:PartA
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• v.16A no.5
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• pp.319-326
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• 2009

Since string operations were applied to computational biology area, various data structures and algorithms for computing efficient string operations have been studied. The longest common substring problem is an operation to find the longest matching substring in more than two strings, and maximal repeat of string problem is an operation to find substrings repeated more than once in the given string. These operations are importantly used in the string processing area such as pattern matching and likelihood measurement. In this paper, we present algorithms to compute the longest common substring of two strings and to find the maximal repeat of string using three-dimensional $n{\times}n{\times}n$ processors on RMESH(Reconfigurable MESH). Our algorithms have O(1) time complexity.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.171-174
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• 2003

In this paper, a Learning module for a reconfigurable neural network processor(ERNIE) was proposed for an On-chip learning. The existing reconfigurable neural network processor(ERNIE) has a much better performance than the software program but it doesn't support On-chip learning function. A learning module which is based on Back Propagation algorithm was designed for a help of this weak point. A pipeline structure let the learning module be able to update the weights rapidly and continuously. It was tested with five types of alphabet font to evaluate learning module. It compared with C programed neural network model on PC in calculation speed and correctness of recognition. As a result of this experiment, it can be found that the neural network processor(ERNIE) with learning module decrease the neural network training time efficiently at the same recognition rate compared with software computing based neural network model. This On-chip learning module showed that the reconfigurable neural network processor(ERNIE) could be a evolvable neural network processor which can fine the optimal configuration of network by itself.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.8
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• pp.1368-1387
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• 2011

In recent years, ubiquitous and pervasive scenarios have emerged as a complex ecosystem where differentiated software/hardware components interoperate wirelessly and seamlessly. The goal is to enable users to continuously access services and contents, and to always get the best out of their current environment and available resources. In such dynamic and flexible scenarios, the need emerges for flexible and general solutions for continuous runtime self-reconfiguration and self-optimization of ubiquitous support software systems. This paper proposes a fully reconfigurable middleware approach that aims at reconfiguring complex software systems made up of heterogeneous off-the-shelf components from both functional and non-functional perspectives. Our middleware can also extend already existing and non-reconfigurable middleware/applications in an easy and flexible way, with no need to re-design them. The proposed design principles have been practically applied to the implementation of a runtime self-reconfigurable middleware called Off-The-Shelf Ready To Go (OTS-RTG), implemented on top of iPOJO. The reported experimental results both exhibit a limited overhead and show the wide applicability of the proposed solution to many application scenarios, including complex, industrial, Enterprise Service Bus-based ones.

• Journal of Internet Computing and Services
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• v.7 no.2
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• pp.121-136
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• 2006

Software architecture and protocols to be maintained between components for the reconfigurable SDR system is analyzed and suggest system design idea for the implementation of software. To do this, related surveys are reviews and set up the system model with the structure of embedded system. SDR system architecture is suggested with five layered structure, consisted with hardware, operating system, middle-ware, service objects and application layer. SDR system is designed to be work on the basis of Linux operating system, and aimed to be scalable and reconfigurable. It is introduced the design result of software protocol and state transition diagram for the implementations of software download function which is the most important feature in SDR.

• ETRI Journal
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• v.45 no.1
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• pp.28-44
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• 2023

We propose short packet communication in an underlay cognitive radio network assisted by an intelligent reflecting surface (IRS) composed of multiple reconfigurable reflectors. This scheme, called the IRS protocol, operates in only one time slot (TS) using the IRS. The IRS adjusts its phases to give zero received cumulative phase at the secondary destination, thereby enhancing the end-to-end signal-to-noise ratio. The transmitting power of the secondary source is optimized to simultaneously satisfy the multi-interference constraints, hardware limitations, and performance improvement. Simulation and analysis results of the average block error rates (BLERs) show that the performance can be enhanced by installing more reconfigurable reflectors, increasing the blocklength, lowering the number of required primary receivers, or sending fewer information bits. Moreover, the proposed IRS protocol always outperforms underlay relaying protocols using two TSs for data transmission, and achieves the best average BLER at identical transmission distances between the secondary source and secondary destination. The theoretical analyses are confirmed by Monte Carlo simulations.

• ETRI Journal
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• v.39 no.5
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• pp.632-642
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• 2017

Digital all-optical parallel computing is an important research direction and spans conventional devices and convergent nano-optics deployments. Optical bus-based interconnects provide interesting aspects such as relative information communication speed-up or slow-down between optical signals. This aspect is harnessed in the newly proposed All-Optical Linear Array with a Reconfigurable Pipelined Bus System (OLARPBS) model. However, the physical realization of such communication interconnects needs to be considered. This paper considers spatial layouts of processing elements along with the optical bus light paths that are necessary to realize the corresponding interconnection requirements. A metric in terms of the degree of required physical constraint is developed to characterize the variety of possible solutions. Simple algorithms that determine spatial layouts are given. It is shown that certain communication interconnection structures have associated intrinsic topologies.

• Journal of the Optical Society of Korea
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• v.16 no.1
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• pp.13-16
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• 2012

We demonstrate an optical gate architecture using a single SOA to perform AND, OR and NOT logic functions. Simple reconfigurable all-optical logic operations are implemented using RZ modulated signals at 40 Gb/s. Contrast ratio and extinction ratio values have been analysed for the different types of logic gates. Maximum extinction ratio and contrast ratio achieved are 19dB and 17.2 dB respectively. Simple structure and potential for integration makes this architecture an interesting approach in photonic computing and optical signal processing.

• Journal of KIISE:Computing Practices and Letters
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• v.10 no.1
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• pp.49-56
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• 2004

Load imbalance is a serious impediment to achieving good performance in parallel processing. Global load balancing schemes cannot adequately manage to balance parallel tasks generated from a single application. Dynamic loop scheduling methods are known to be useful in balancing parallel loops on shared-memory multiprocessor machines. However, their centralized nature causes a bottleneck for the relatively small number of processors in a network of workstations because of order-of-magniture differences in communication overheads. Moreover, improvements of basis loops scheduling methods have not effectively dealt with irregularly distributed workloads in parallel loops, which commonly occur in applications for a network of workstation. In this paper, we present a new reconfigurable and decentralized balancing method for parallel loops on a network of workstations. Since our method supplements performance balancing with those tranditional load balancing methods, it minimizes the overall execution time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.485-492
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• 2008

Computers used fer light-weight computing environments are considerably limited in resources and performance running in ubiquitous environment. Because of the limited resources, it is difficult to apply existing security technologies to the light-weight computers. In this paper, light-weight security software is implemented using RC-5 encryption and SHA-1 authentication algorithm which is appropriate for light-weight computing environments. The design of components based on security software of a light-weight computer application and the test-bed for security software are presented. The simulation verifies the correctness of the security software. The architecture of the light-weight and reconfigurable security software for light-weight computer applications is proposed. The proposed security software is small size and provides reconfigurable security library based on the light-weight component and the software manager that configures software platform is loaded with the library at the time it is needed.