• 정보와 통신
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• 제19권11호
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• pp.70-84
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• 2002

In this paper we discuss a multi-threaded baseband Processor capable of executing all physical layer processing of high data rate communications systems completely in software. We discuss the enabling technology for a software defined radio approach and present results for GPRS. 802.11b, and 2Mbps WCDMA. All of these protocols can be executed in real-time on the SB9600 chip using the Sandblaster core.

• 한국통신학회논문지
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• 제35권11B호
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• pp.1659-1666
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• 2010

고기동 유도탄들은 다양한 탄내 인터페이스와 빠른 유도 조종 루프를 가진다. 그러므로 Hardware-in-the-Loop(HWIL) 시뮬레이션 제어 시스템은 고성능의 연산기능 및 하드웨어 인터페이스 기능을 가져야 하며, 실시간 운영체제, 임베디드 시스템, 자료 통신, 실시간 하드웨어 제어와 같이 다양한 IT 분야를 융합하여 개발되어야 한다. 이 논문은 고기동 유도탄의 HWIL 시뮬레이션을 수행하기 위한 제어 시스템 설계 기법으로 시스템 하드웨어 구성, 고성능의 다중 프로세서를 사용하기 위한 업무 할당 알고리즘, HWIL 시뮬레이션 실시간 연산 및 제어 기법, 프로세서 통신 기법, 실시간 자료 획득 기법을 제시한다.

• Applied Microscopy
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• 제46권1호
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• pp.6-13
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• 2016

Fluorescence lifetime imaging microscopy (FLIM) has been considered an effective technique to investigate chemical properties of the specimens, especially of biological samples. Despite of this advantageous trait, researchers in this field have had difficulties applying FLIM to their systems because acquiring an image using FLIM consumes too much time. Although analog mean-delay (AMD) method was introduced to enhance the imaging speed of commonly used FLIM based on time-correlated single photon counting (TCSPC), a real-time image reconstruction using AMD method has not been implemented due to its data processing obstacles. In this paper, we introduce a real-time image restoration of AMD-FLIM through fast parallel data processing by using Threading Building Blocks (TBB; Intel) and octa-core processor (i7-5960x; Intel). Frame rate of 3.8 frames per second was achieved in $1,024{\times}1,024$ resolution with over 4 million lifetime determinations per second and measurement error within 10%. This image acquisition speed is 184 times faster than that of single-channel TCSPC and 9.2 times faster than that of 8-channel TCSPC (state-of-art photon counting rate of 80 million counts per second) with the same lifetime accuracy of 10% and the same pixel resolution.

• Journal of international Conference on Electrical Machines and Systems
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• 제3권4호
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• pp.428-432
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• 2014

Rotating machines are an integral part of large electrical power machinery in most of the industries. Any degradation or outages in the rotating electric machinery can result in significant losses in productivity. It is critical to monitor the equipment for any degradation's so that it can serve as an early warning for adequate maintenance activities and repair. Prior research and field studies have indicated that the rotating machines have a particular type of signal structure during the initial start-up transient. A machine performance can be studied based on the effect of degradation in signal parameters. In this paper a data-acquisition system and the FFT algorithm has been design and model using the MATLAB and Simulink. The implementation had been carried out on the TMS320 DSP Processor and various testing and verification of the machine performance had been carried out. The results show good agreement with expected results for both simulated and real-time data. The real-time data from AC water pumps which have rotating motors built-in were collected and analysed. The FFT algorithm provides frequency response and based on this frequency response performance of the machine had been measured.The FFT algorithm provides only approximation about the machine performances.

• 전자공학회논문지C
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• 제34C권7호
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• pp.28-37
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• 1997

In this paper, we designed a motion estimator for MPEG-2 video coder using VHDL. Motion estimation is indispensable for encoding MPEG 2 video. Motion estimation takes over 50% computation power of video encoding 37 frames per second and is suitable for real-time processing. The number of data accesses for computation is fewer than 2 times compared with that of old one. This makes slower memory module available. We minimize input pins to migrate input data through PEs. This processor can compute various motio estimation modes at one calculation that is supported by MPEG-2 video standard. Also independent control architecture makes this processor a single processor or a sub module in amultimedia chip.

• 디지털산업정보학회논문지
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• 제8권1호
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• pp.117-123
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• 2012

This paper implements mobile Worldwide Interoperability for Microwave Access (WiMAX) receiver using Software Defined Radio (SDR) technology. SDR system is difficult to implement on the mobile handset because of restrictions that are computing power and under space constraints. The implemented receiver processes mobile WiMAX software modem on Open Multimedia Application Platform (OMAP) System on Chip (SoC) and Field Programmable Gate Array (FPGA). OMAP SoC is composed of ARM processor and Digital Signal Processor (DSP). ARM processor supports Single Instruction Multiple Data (SIMD) instruction which could operate on a vector of data with a single instruction and DSP is powerful image and video accelerators. For this reason, we suggest the possibility of SDR technology in the mobile handset. In order to verify the performance of the mobile WiMAX receiver, we measure the software modem runtime respectively. The experimental results show that the proposed receiver is able to do real-time signal processing.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
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• pp.2315-2318
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• 2003

The Wavelet Transform has been applied in mathematics and computer sciences. Numerous studies have proven its advantages in image processing and data compression, and have made it a basic encoding technique in data compression standards like JPEG2000 and MPEG-4. Software implementations of the Discrete Wavelet Transform (DWT) appears to be the performance bottleneck in real-time systems in terms of performance. And hardware implementations are not flexible. Therefore, FPGA implementations of the DWT has been a topic of recent research. The goal of this thesis is to investigate of FPGA implementations of the DWT Processor for image compression applications. The DWT processor design is based on the Lifting Based Wavelet Transform Scheme, which is a fast implementation of the DWT The design uses various techniques. The DWT Processor was simulated and implemented in a FLEX FPGA platform of Altera

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.257-258
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• 2006

In this paper, we address several issues in the real time implementation of MPEG-1 Layer II decoder on a fixed-point digital signal processor (DSP), especially TMS320C6416. There is a trade-off between processing speed and the size of program/data memory for the optimal implementation. In a view of the speed optimization, we first convert the floating point operations into fixed point ones with little degradation in audio quality, and then the look-up tables used for the inverse quantization of the audio codec are forced to be located into the internal memory of the DSP. And then, window functions and filter coefficients in the decoder are precalculated and stored as constant, which makes the decoder faster even larger memory size is required. It is shown from the real-time experiments that the fixed-point implementation enables us to make the decoder with a sampling rate of 48 kHz operate with 3 times faster than real-time on TMS320C6416 at a clock rate of 600 MHz.

• 융합신호처리학회논문지
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• 제3권1호
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• pp.27-32
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• 2002

본 논문에서 제안한 텔레미트리 시스템은 생체신호를 중거리로 전송하기 위한 RF 송신기와 전자파 간섭의 영향이 없는 광을 매체로한 수신기이다. 텔레미트리 시스템은 of 65$\times$125$\times$45mm크기이며, RF 송신부, 광 수신부와 생체신호 처리를 위한 CMOS 칩으로 구성되어 있다. 제안된 텔레메트리 장점은 전자파에 노출을 최소화하면서 중거리(50m) 텔레메트리가 가능하여, 자유로운 상태에서의 모니터링이 가능하다. 관측 시스템은 실시간 처리를 위해 dual-processor구조로 설계했다. 본 연구에서는 1 채널 360Hz, 16 Bits의 심전도 데이터를 1.42초 간격으로 실시간 웨이브렛 변환할 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.105-108
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• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.