• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.11a
• /
• pp.363-363
• /
• 2008

The development of dry etching process for sapphire wafer with plasma has been key issues for the opto-electric devices. The challenges are increasing control and obtaining low plasma induced-damage because an unwanted scattering of radiation is caused by the spatial disorder of pattern and variation of surface roughness. The plasma-induced damages during plasma etching process can be classified as impurity contamination of residual etch products or bonding disruption in lattice due to charged particle bombardment. Therefor, fine pattern technology with low damaged etching process and high etch rate are urgently needed. Until now, there are a lot of reports on the etching of sapphire wafer with using $Cl_2$/Ar, $BCl_3$/Ar, HBr/Ar and so on [1]. However, the etch behavior of sapphire wafer have investigated with variation of only one parameter while other parameters are fixed. In this study, we investigated the effect of pressure and other parameters on the etch rate and the selectivity. We selected $BCl_3$ as an etch ant because $BCl_3$ plasmas are widely used in etching process of oxide materials. In plasma, the $BCl_3$ molecule can be dissociated into B radical, $B^+$ ion, Cl radical and $Cl^+$ ion. However, the $BCl_3$ molecule can be dissociated into B radical or $B^+$ ion easier than Cl radical or $Cl^+$ ion. First, we evaluated the etch behaviors of sapphire wafer in $BCl_3$/additive gases (Ar, $N_2,Cl_2$) gases. The behavior of etch rate of sapphire substrate was monitored as a function of additive gas ratio to $BCl_3$ based plasma, total flow rate, r.f. power, d.c. bias under different pressures of 5 mTorr, 10 mTorr, 20 mTorr and 30 mTorr. The etch rates of sapphire wafer, $SiO_2$ and PR were measured with using alpha step surface profiler. In order to understand the changes of radicals, volume density of Cl, B radical and BCl molecule were investigated with optical emission spectroscopy (OES). The chemical states of $Al_2O_3$ thin films were studied with energy dispersive X-ray (EDX) and depth profile anlysis of auger electron spectroscopy (AES). The enhancement of sapphire substrate can be explained by the reactive ion etching mechanism with the competition of the formation of volatile $AlCl_3$, $Al_2Cl_6$ or $BOCl_3$ and the sputter effect by energetic ions.

• Journal of the Korean institute of surface engineering
• /
• v.34 no.5
• /
• pp.516-521
• /
• 2001

Dry etching of Si wafer and $SiO_2$ layers was performed using He/Cl$_2$ mixture plasma by diode-type reactive ion etcher (RIE) system. For Si etching, the Cl molecules react with the Si molecules on the surface and become chemically stable, indicating that the reactants need energetic ion bombardment. During the ion assisted desorption, energetic ions would damage the photoresist (PR) and produce the bad etch Si-profile. Moreover, we have examined the characteristics of the Cl-Si reaction system, and developed the new fabrication procedures with a $Cl_2$/He mixture for Si and $SiO_2$-etching. The developed novel fabrication procedure allows the RIE to be unexpensive and useful a Si deep etching system. Since the etch rate was proved to increase linearly with fHe and the selectivity of Si to $SiO_2$ etch rate was observed to be inversely proportional to fHe.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.13 no.12
• /
• pp.996-1002
• /
• 2000

Ferroelectric (Ba, Sr) TiO$_3$(BST) thin films have attracted much attention for use in new capacitor materials of dynamic random access memories (DRAMs). In order to apply BST to the DRAMs, the etching process for BST thin film with high etch rate and vertical profile must be developed. However, the former studies have the problem of low etch rate. In this study, in order to increase the etch rate, BST thin films were etched with a magnetically enhanced inductively coupled plasma(MEICP) that have much higher plasma density than RIE (reactive ion etching) and ICP (inductively coupled plasma). Experiment was done by varying the etching parameters such as CF$_4$/(CF$_4$+Ar) gas mixing ratio, rf power, dc bias voltage and chamber pressure. The maximum etch rate of the BST films was 170nm/min under CF$_4$/CF$_4$+Ar) of 0.1, 600 W/-350 V and 5 mTorr. The selectivities of BST to Pt and PR were 0.6 and 0.7, respectively. Chemical reaction and residue of the etched surface were investigated with X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS).

• Progress in Superconductivity
• /
• v.12 no.2
• /
• pp.114-117
• /
• 2011

We report our efforts on the development of Nb-based non-hysteretic Josephson junction fabrication process for quantu device applications. By adopting and modifying the existing Nb-aluminum oxide tunnel junction process, we develop a process for non-hysteretic Josephson junction circuits using metal-silicide as metallic barrier material. We use sputter deposition of Nb and $MoSi_2$, PECVD deposition of silicon oxide as insulator material, and ICP-RIE for metal and oxide etch. The advantage of the metal-silicide barrier in the Nb junction process is that it can be etched in $SF_6$ RIE together with Nb electrode. In order to define a junction area precisely and uniformly, end-point detection for the RIE process is critical. In this paper, we employed thin Al layer for the etch stop, and optimized the etch condition. We have successfully demonstrated that the etch stop properties of the inserted Al layer give a uniform etch profile and a precise thickness control of the base electrode in Nb trilayer junctions.

• Proceedings of the KIEE Conference
• /
• 2001.07c
• /
• pp.1890-1892
• /
• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -750 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.21 no.8
• /
• pp.711-714
• /
• 2008

Metal-oxide-semiconductor (MOS) capacitors were fabricated to investigate the plasma damage caused by reactive ion etching (RIE) on (100) oriented silicon-on-insulator (SOI) substrates. The thickness of the top-gate oxide, SOI, and buried oxide layers were 10 nm, 50 nm, and 100 nm, respectively. The MOS/SOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching. The measured C-V curves were compared to the numerical results from corresponding 2-dimensional (2-D) structures by using a Silvaco Atlas simulator.

• Journal of the Korean Vacuum Society
• /
• v.7 no.2
• /
• pp.161-168
• /
• 1998

Reactive ion etching process for InGaAs/InP using the CH4/H2 high density inductively coupled plasma was investigated. The experimental design method proposed by Taguchi was utilized to cover the whole parameter range while maintaining reasonable number of actual experiments. Results showed that the ICP power mainly affects surface roughness and verticality of the sidewall, bias power does etch rate and verticality, CH4 gas concentraion does the verticality and etch rate, and the distance between the induction coil and specimen mostly affects the surface roughness. It was also observed that the chamber pressure is the dominant parameter for the etch rate and verticality of the sidewall. The optimum condition was ICP power 700W, bias power 150 W, 15% $CH_4$, 7.5 mTorr, and 14 cm distance, resulting in about 3 $\mu\textrm{m}$/hr etch rate with smooth surfaces and vertical mesa sidewalls.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1993.05a
• /
• pp.45-45
• /
• 1993

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2006.05a
• /
• pp.27.2-27.2
• /
• 2006

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2015.05a
• /
• pp.38-38
• /
• 2015

차세대 메모리로 각광받고 있는 STT-MRAM의 동작특성을 향상시키기 위하여 식각 시 재 증착되는 식각 부산물을 저 손상을 제거하였다.