• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.492-494
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• 2006

Neutral line current is analyzed by the neutral line CF in nonlinear load balanced and unbalanced conditions. The worst nonlinear load condition is nonlinear balanced load condition, and It is below CFNL=1.194 that a neutral line current could not excess the rated value

• Proceedings of the KIEE Conference
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• 2005.10c
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• pp.155-157
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• 2005

This paper analyzed the adoption possibility of a low cost single phase active power filter as the neutral current reduction device in three-phase four-wire power system with the balanced or/and unbalnaced nonlinear load conditions. Proposed system can make neutral line current to within rated vale without the phase current THD change of the installed phase line.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.328-332
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• 2010

The SLF(Short Line Fault) breaking capability test for high voltage class $SF_6$ GCB(Gas Circuit Breaker) was conducted. Simplified LC resonant circuit test facility was used for SLF breaking test. During test, Test current was measured by Rogwski coil and arc voltage was measured by voltage divider. Arc conductance was calculated by using these test results before 200ns at current zero. Critical arc conductance value at rated voltage 145kV class is about 2.3mS regardless of breaking current magnitude and arc conductance value at rated voltage 170kV class is about 2.6mS.

• Proceedings of the KIEE Conference
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• 2008.11b
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• pp.109-109
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• 2008

Neutral line current is analyzed by the neutral line CF in nonlinear load balanced and unbalanced conditions. The worst nonlinear load condition is nonlinear balanced load condition. and It is below CFNL=1.194 that a neutral line current could not excess the rated value.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.371-371
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• 2009

For the application of superconducting wires to fault current limiting devices, it is required that they have a high rated voltage when a fault occurs. Stabilizer-free coated conductors, particularly, shows a good performance for the high rated voltage, which is beyond 0.6 V/cm. In this study, using the stabilizer-free coated conductors, we made fault current limiting devices and examined their characteristics. Fault current limiting devices were fabricated with a shape of the cylinder of a mono-filar coil winding. Stabilizer-free coated conductors were wound along the mono-filar coil line and the terminal parts between the wire and metal were soldered using In solder. Two kinds of devices were fabricated by a different method in the terminal joint, one was made by a soldering and the other was made by a soldering-free joint. Critical currents and resistance at the joint parts were measured. In addition, long-time current flowing tests were also carried out for the characterization of the fault current limiting devices.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.48-49
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• 2011

A new LCL filter design of a PCS with the consideration of fault current minimization is proposed. The magnitude of fault current is analysed with the variation of inverter side $L_i$, line side $L_u$, and filter capacitor $C_f$ under constant line side $THD_i$ of 5%. It is found that inverter side fault current reaches up to 200%~660% of the rated current with the variation of $L_i$. It is expected that the results can be applied to the detailed design of PCS filter.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.1
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• pp.81-90
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• 2015

This paper investigates the droop control-based real and reactive power load sharing with a virtual inductor when the line impedance between inverter and Point of Common Coupling (PCC) is partly and unequally resistive in high-capacity systems. In this paper, the virtual inductor method is applied to parallel inverter systems with resistive and inductive line impedance. Reactive power sharing error has been improved by applying droop control after considering each line impedance voltage drop. However, in high capacity parallel systems with large output current, the reference output voltage, which is the output of droop controller, becomes lower than the rated value because of the high voltage drop from virtual inductance. Hence, line impedance voltage drop has been added to the droop equation so that parallel inverters operate within the range of rated output voltage. Additionally, the virtual inductor value has been selected via small signal modeling to analyze stability in transient conditions. Finally, the proposed droop method has been verified by MATLAB and PSIM simulation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.8
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• pp.1163-1171
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• 2017

The problem of fault current to exceed the rated capacity of a power circuit breaker can cause a serious accident to hurt the reliability of the power system. In order to solve this issue, current limiting reactors and circuit breakers with increased capacity are utilized but these solutions have some technical limitations. Back-to-back high voltage direct current(BTB HVDC) may be applied for reducing the fault current. When BTB HVDCs are installed for reduction in fault current, selecting the optimal location of the BTB HVDC without causing overload of line power becomes a key point. In this paper, we use genetic algorithm to find optimal location effectively in a short time. We propose a new methodology for determining the BTB HVDC optimal location to reduce fault current without causing overload of line power in metropolitan areas. Also, the procedure of performing the calculation of fault current and line power flow by PSS/E is carried out automatically using Python. It is shown that this optimization methodology can be applied effectively for determining the BTB HVDC optimal location to reduce fault current without causing overload of line power by a case study.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.605-607
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• 2001

In this paper, an off-tine UPS with CVT(constant voltage transformer) is designed and the experimental result and problems of the designed UPS is given and discussed. This off-line UPS consists of triple-port CVT and PWM inverter which acts as charger and inverter. It can be evaluated in low price because haying simple structure. It offers high performance because CVT restricts the short current automatically about two or three times of rated current, has nearly unit power factor and constant output voltage to varying input voltage. The weak points of this UPS are that the output voltage waveform is not perfect sinusoidal and has phase difference to input voltage. The experimental result and problems of the designed UPS is given.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.1
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• pp.91-98
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• 1999

An integrated ZCS quasi-resonant converter(QRC) for the power factor correction with a single switch is presented in this paper. The power factor correction can be achieved by the discontinuous conduction mode(DCM) operation of the input current. The proposed converter gives the good power factor, low line current harmonics, and tight output regulation. The input current waveform of the prototype designed using design equations shows about 15% of total harmonic distortion at rated condition. Also, the efficiency and power factor can be obtained about 86% and 0.985, respectively, at rated condition. The proposed converter is suitable for a low power level converter with a tightly regulated low output voltage and switching frequency of more than several hundreds kHz.