• Title/Summary/Keyword: RV32IC

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A Design and Implementation of 32-bit Pipeline RISC-V Processor Supporting Compressed Instructions for Memory Efficiency (메모리 효율성을 높이기 위한 압축 명령어를 지원하는 32-비트 파이프라인 RISC-V프로세서 설계 및 구현)

  • Hyeonjin Sim;Yongwoo Kim
    • Journal of the Semiconductor & Display Technology
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    • v.23 no.3
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    • pp.7-13
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    • 2024
  • With the development of technologies such as the Internet of Things (IoT) and autonomous vehicles, research is being conducted on embedded processors that meet high performance, low power, and memory efficiency. The "C" expansion of the RISC-V processor is required to increase memory efficiency. In this paper, we propose an RV32IC processor and compare the benchmark performance score of the RV32I processor with the code size generated by the GCC compiler. In addition, we propose memory access and combination methods to support 16-bit compression commands, and command extension methods. The proposed RV32IC processor satisfies the maximum operating frequency of 50 MHz on the Artix-7 FPGA. The performance was checked using the benchmark programs of the Dhrystone and Coremark, and the code sizes of the RV32I and RV32IC generated by the GCC compiler were compared. The proposed processor RV32IC decreased DMIPS/MHz by 2.72% and Coremark/MHz by 0.61% compared to RV32I, but Coremark's code size decreased by 14.93%.

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