• Journal of Broadcast Engineering
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• v.18 no.6
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• pp.927-934
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• 2013

This paper aims to realize a Signal to Noise Ratio Estimator which constitutes a critical index of the broadcasting system in OFDM system with a synchronized type based on ISDB-T system. Of the elements which are comprising OFDM segments of ISDB-T system using the MSE algorithm suitable for ASIC design owing to its low complexity among a diverse SNR estimation methods, SNR estimation method using the broadcasting information data and the SNR estimation method using scattered pilot signal were realized by RTL. These two methods were compared in terms of their performance through simulation test not only in the AWGN channel which is an ideal channel, but also in SFN channel and frequency selective fading channel, which are distorted channels. Complexity of two methods were also compared through RTL realization. As a result of this comparison analysis, it was concluded that the SNR estimation method using scattered pilot signal shows more excellent performance and easiness in realization.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.2
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• pp.352-359
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• 2008

RTLS(Real Time Location Systems) is a technology that identifies a location of a target object and provides peat visibility at a work place. Unlike those of the overseas, domestic ports and shipyards have narrow work places and thus, the efficient utilization of these spaces is one of the most important considerations for improving productivity. Companies considering implementation of RTLS should understand its limitations or applicability. In this paper, problems of RTLS such as fading factors which were caused from the features of RF, and limitations caused from the preconditions of RTLS were explained. To overcome those problems, three types of solutions such as movable RTLS, semi-movable RTLS and combined RTLS with other technologies were suggested.

• International Journal of Aeronautical and Space Sciences
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• v.18 no.4
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• pp.675-687
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• 2017

In the aerospace industry, we have produced various models according to operational conditions and the environment after development of the base model is completed. Therefore, when design change is necessary, there are modification and updating costs of the circuit whenever environment variables change. For these reasons, recently, in various fields, system designs that can flexibly respond to changing environmental conditions using field programmable gate arrays (FPGAs) are attracting attention, and the rapidly changing aerospace industry also uses FPGAs to organize the system environment. In this paper, we design the controller area network (CAN) intellectual property (IP) protocol used instead of the avionics protocol that includes ARINC-429 and MIL-STD-1553, which are not suitable for small unmanned aerial vehicle (UAV) systems at the register transistor logic (RTL) level, which does not depend on the FPGA vender, and we verify the performance. Consequentially, a Spartan 6 FPGA model-based system on chip (SoC) including an embedded system is constructed by using the designed CAN communications IP and Xilinx Microblaze, and the configured SoC only recorded an average 32% logic element usage rate in the Spartan 6 FPGA model.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4A
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• pp.401-407
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• 2010

As according to utilizing mobile devices, the real time locating system to provide high quality service is required. RTLS based on wireless communication can be damaged from radio shadow areas which guarantee the line of sight. To cope with the radio shadow area, this paper proposes the performance improvement method using assistant tags and a directional antenna based reader. In addition, this paper also provides the design and implementation of RTLS and experiments for performance evaluation. The result shows that a success rate is increased up to 38% and accuracy is a CEP of 1.13 meters.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.719-721
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• 2013

A thinning stage of fingerprint algorithm occupies 39% cycle of microprocessor system for identification processing of image from fingerprint sensor. Hardware block processing is more effective than software one in speed and power consumption, because a thinning algorithm is iteration of simple instructions without a transcendental function. This paper describes an effective hardware scheme for thinning stage processing using Verilog-HDL in $64{\times}64$ Pixel Array. The hardware scheme is designed and simulated in RTL. The logic is also synthesized by XST in FPGA environment and tested. Experimental results show the performance of the proposed scheme and possibility of application for a soft microprocessor and thinning processor embedded fingerprint SoC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.106-114
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• 2010

We proposed an unified design methodology and verification platform for giga-scale System on Chip (SoC). According to the growth of VLSI integration, the existing RTL design methodology has a limitation of a production gap because a design complexity increases. A verification methodology need an evolution to overcome a verification gap. The proposed platform includes a high level synthesis, and we develop a power-aware verification platform for low power design and verification automation using it's results. We developed a verification automation and power-aware verification methodology based on control and data flow graph (CDFG) and an abstract level language and RTL. The verification platform includes self-checking and the coverage driven verification methodology. Especially, the number of the random vector decreases minimum 5.75 times with the constrained random vector algorithm which is developed for the power-aware verification. This platform can verify a low power design with a general logic simulator using a power and power cell modeling method. This unified design and verification platform allow automatically to verify, design and synthesis the giga-scale design from the system level to RTL level in the whole design flow.

• Electronics and Telecommunications Trends
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• v.27 no.5
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• pp.36-43
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• 2012

본고에서는 멀티미디어 응용을 위한 멀티 코어 가상 플랫폼 설계 및 검증 방법에 대해서 기술한다. 최근에 멀티미디어 응용인 MPEG-4, H.264, HEVC(High Efficiency Video Coding), 3D 및 홀로그램과 같은 대용량 데이터를 처리하기 위해 다수 개의 코어로 구성된 멀티 코어 플랫폼을 사용한다. 기존의 RTL(Register Transfer Level) 기반의 멀티 코어 플랫폼에서 멀티미디어 응용을 설계하고 검증하는데 시뮬레이션 시간에 의한 제약 사항이 존재한다. 이를 해결하기 위해 시스템 수준에서 하드웨어의 SW 모델로 구성된 가상 플랫폼을 사용한다. 가상 플랫폼은 기존의 RTL 플랫폼보다 100~200배 빠른 고속 시뮬레이션이 가능하므로 멀티미디어 응용에 따른 성능 분석 및 구조 탐색을 통해서 시스템 성능을 향상 시킬 수 있다. 본고에서는 8~32개 멀티 코어 가상 플랫폼에 H.264 디코더를 적용하여 성능 분석하는 방법과 실험 결과에 대해서 기술한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.6
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• pp.1078-1082
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• 2001

This is an example of ABSTRACT format. We made a HTTP server using 8 bit microprocessor It was TMP84c015 which applied a z80 core and RTL8019AS was installed for an ethernet physical layer. Assembly language was used to optimized a performance of the MPU, to overcome an restriction of memory sire and to maximize the throughput of packet using TCP, UDP, IP, ICMP, ARP protocol. We used LabVIEW to verify the each protocol on the client side.

• Journal of information and communication convergence engineering
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• v.8 no.5
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• pp.570-574
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• 2010

A thinning algorithm changes a binary fingerprint image to one pixel width. A thinning stage occupies 40% cycle of 32-bit RISC microprocessor system for a fingerprint identification algorithm. Hardware block processing is more effective than software one in speed, because a thinning algorithm is iteration of simple instructions. This paper describes an effective hardware scheme for thinning stage processing using the Verilog-HDL in $160\times192$ Pixel Array. The ZS algorithm was applied for a thinning stage. The hardware scheme was designed and simulated in RTL. The logic was also synthesized by XST in FPGA environment. Experimental results show the performance of the proposed scheme.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.561-562
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• 2008

In this paper, we propose a establishment of system level environment to exploit PC system with SSD (Solid State Disk) by using TLM (Transaction Level Modeling) method with SystemC language. The reason why we choose this modeling method is that it eases RTL (Register Transfer Level) modeling burdens and we can accurately estimate the performance about different architectural changes. Also, it provides simulation speed which is relatively faster than RTL modeling method. The baseline architectural platform we implemented showed that SSD's internal transfer time is a dominant factor, so we need to improve that part and it is expected to be a good simulator to measure the system's overall performance by exploiting SSD's internal architectures.