• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.12 no.1
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• pp.62-68
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• 1999

Ferroelectric $Sr_{0.7}/B_{2.3}(Ta_{1-x}Nb_x)_2O_9$(x=0, 0.1, 0.2, 0.3) thin films were deposited on $Pt/SiO_2/Si$ substrate by MOD(Metalorganic Decomposition) process. Metal carboxylate and metal alkoxide were used as precursors, and 2-methoxyethanol, xylene as solvents. After spin coating, thin films were pre-annealed at $400^{\circ}C$, followed by RTA(Rapid Thermal Annealing) and final annealing at $800^{\circ}C$ in oxygen atmosphere. These procedures were repeated three times to obtain thin films with the thickness of $2000{\AA}$. To enhance the nucleation and growth of layered-perovskite phase, thin films were rapid-thermally annealed above $720^{\circ}C$ in oxygen atmosphere. As RTA temperature increased, fluorite phase was transformed to layered-perovskite phase. And the change of Nb contents affected dielectric / electrical properties and microstructure. The ferroelectric characteristics of $Sr_{0.7}/B_{2.3}(Ta_{1-x}Nb_x)_2O_9$ thin film were Pr=8.67 $\mu{C}/cm^2$, Ec=62.4kV/cm and $I_{L}=1.4\times10^{-7}A/cm^2$ at the applied voltage of 5V, respectively.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.29 no.2
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• pp.50-53
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• 2019

In this study, polycrystalline silicon thin film useful for the solar cells was fabricated by AIC(Aluminum Induced Crystallization) process. A diffusing barrier for this process is prepared with $Al_2O_3$. For the maximization of the grain size of the polycrystalline silicon, a selective blasting of the $Al_2O_3$ diffusing barrier was conducted before annealing treatment. The heat treatment for the activation of the amorphous-Si (a-Si) layer was carried out with Rapid Thermal Annealing (RTA) process. Crystallization of the a-Si layer was analyzed with XRD. It was confirmed that a-Si was crystallized at $500^{\circ}C$ and the silicon crystal is observed to be formed and the grain size of the polycrystalline silicon was observed to be $15.9{\mu}m$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.859-864
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• 2003

We prepared SOI(silicon-on-insulator) wafer pairs of Si II SiO$_2$/Si$_3$N$_4$ II Si using wafer direct bonding with an electric furnace annealing(EFA), a fast linear annealing(FLA), and a rapid thermal annealing(RTA), respectively, by varying the annealing temperatures at a given annealing process. We measured the bonding area and the bonding strength with processes. EFA and FLA showed almost identical bonding area and theoretical bonding strength at the elevated temperature. RTA was not bonded at all due to warpage, We report that FLA process was superior to other annealing processes in aspects of surface temperature, annealing time, and bonding strength.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.4
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• pp.367-370
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• 2004

We fabricated SiGe BiCMOS devices, which are important for ultra high speed RF IC chips, by employing $0.35\mu{m}$ CMOS process. To meet with the requirement of low noise level with linear base leakage current at low VBE region, we try to minimize polysilicon/ silicon interface traps by optimizing capping silicon thickness and EDR(emitter drive-in RTA) temperature. We employed $200\AA$and $300\AA$-thick capping silicon, and varied the EDR process condition at temperature of $900-1000^\circ{C}$, and time of 0-30 sec at a given capping silicon thickness. We investigated current gain behavior at each process condition. We suggest that optimum EDR process condition would be $975^\circ{C}$-30 sec with $300\AA$-thick capping silicon for proposed $0.35\mu{m}$-SiGe HBT devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.16-22
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• 2002

This paper suggests the optimum processing conditions for obtaining good quality $P^{+}$-n shallow junctions formed by pre-amorphization and furnace annealing(FA) to reflow BPSG(bore phosphosilicate glass). $BF_2$ions, the p-type dopant, were implanted with the energy of 20keV and the dose of 2$\times$10$^{15}$ cm$^{-2}$ into the substrates pre-amorphized by As or Ge ions with 45keV, 3$\times$$10^{14}$ $cm^{-2}$. High temperature annealings were performed with a furnace and a rapid thermal annealer. The temperature range of RTA was 950~$1050^{\circ}C$, and the furnace annealing was employed for BPSG reflow with the temperature of $850^{\circ}C$ for 40 minutes. To characterize the formed junctions, junction depth, sheet resistance and diode leakage current were measured. Considering the preamorphization species, Ge ion exhibited better results than As ion. Samples preamorphized with Ge ion and annealed with $1000^{\circ}C$ RTA showed the most excellent characteristics. When FA was included, Ge preamorphization with $1050^{\circ}C$ RTA plus FA showed the lowest product of sheet resistance and junction depth and exhibited the lowest leakage currents.

• Korean Journal of Materials Research
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• v.12 no.10
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• pp.820-824
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• 2002

It is of importance to know that the bonding strength and interfacial stress of SOI wafer pairs to meet with mechanical and thermal stresses during process. We fabricated Si/2000$\AA$-SiO$_2$ ∥ 2000$\AA$-SiO$_2$/Si SOI wafer pairs with electric furnace annealing, rapid thermal annealing (RTA), and fast linear annealing (FLA), respectively, by varying the annealing temperatures at a given annealing process. Bonding strength and interfacial stress were measured by a razor blade crack opening method and a laser curvature characterization method, respectively. All the annealing process induced the tensile thermal stresses. Electrical furnace annealing achieved the maximum bonding strength at $1000^{\circ}C$-2 hr anneal, while it produced constant thermal tensile stress by $1000^{\circ}C$. RTA showed very small bonding strength due to premating failure during annealing. FLA showed enough bonding strength at $500^{\circ}C$, however large thermal tensile stress were induced. We confirmed that premated wafer pairs should have appropriate compressive interfacial stress to compensate the thermal tensile stress during a given annealing process.

• Korean Journal of Materials Research
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• v.23 no.7
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• pp.379-384
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• 2013

In order to produce size-controllable Ag nanoparticles and a nanomesh-patterned Si substrate, we introduce a rapid thermal annealing(RTA) method and a metal assisted chemical etching(MCE) process. Ag nanoparticles were self-organized from a thin Ag film on a Si substrate through the RTA process. The mean diameter of the nanoparticles was modulated by changing the thickness of the Ag film. Furthermore, we controlled the surface energy of the Si substrate by changing the Ar or $H_2$ ambient gas during the RTA process, and the modified surface energy was evaluated through water contact angle test. A smaller mean diameter of Ag nanoparticles was obtained under $H_2$ gas at RTA, compared to that under Ar, from the same thickness of Ag thin film. This result was observed by SEM and summarized by statistical analysis. The mechanism of this result was determined by the surface energy change caused by the chemical reaction between the Si substrate and $H_2$. The change of the surface energy affected on uniformity in the MCE process using Ag nanoparticles as catalyst. The nanoparticles formed under ambient Ar, having high surface energy, randomly moved in the lateral direction on the substrate even though the etching solution consisting of 10 % HF and 0.12 % $H_2O_2$ was cooled down to $-20^{\circ}C$ to minimize thermal energy, which could act as the driving force of movement. On the other hand, the nanoparticles thermally treated under ambient $H_2$ had low surface energy as the surface of the Si substrate reacted with $H_2$. That's why the Ag nanoparticles could keep their pattern and vertically etch the Si substrate during MCE.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.130.2-130.2
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• 2013

Today, chemical vapor deposition (CVD) of hydrocarbon gases has been demonstrated as an attractive method to synthesize large-area graphene layers. However, special care should be taken to precisely control the resulting graphene layers in CVD due to its sensitivity to various process parameters. Therefore, a facile synthesis to grow graphene layers with high controllability will have great advantages for scalable practical applications. In order to simplify and create efficiency in graphene synthesis, the graphene growth by thermal annealing process has been discussed by several groups. However, the study on growth mechanism and the detailed structural and optoelectronic properties in the resulting graphene films have not been reported yet, which will be of particular interest to explore for the practical application of graphene. In this study, we report the growth of few-layer, large-area graphene films using rapid thermal annealing (RTA) without the use of intentional carbon-containing precursor. The instability of nickel films in air facilitates the spontaneous formation of ultrathin (<2~3 nm) carbon- and oxygen-containing compounds on a nickel surface and high-temperature annealing of the nickel samples results in the formation of few-layer graphene films with high crystallinity. From annealing temperature and ambient studies during RTA, it was found that the evaporation of oxygen atoms from the surface is the dominant factor affecting the formation of graphene films. The thickness of the graphene layers is strongly dependent on the RTA temperature and time and the resulting films have a limited thickness less than 2 nm even for an extended RTA time. The transferred films have a low sheet resistance of ~380 ${\Omega}/sq$, with ~93% optical transparency. This simple and potentially inexpensive method of synthesizing novel 2-dimensional carbon films offers a wide choice of graphene films for various potential applications.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.7
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• pp.58-72
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• 1989

Rapid thermal annealing system using tungsten halogen lamps and reflectors was developed to get 2 slips per ${\2^'}$ wafer at least at $1300^{\circ}C$. Reflectors are different in reflectance between the edge and the center of an wafer. Slip generation could be suppressed by placing a graphite ring around the wafer. The two-channel heating is proposed as the others solution to reduce the power consumption and the slip generation simultaneously.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1333-1336
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• 1998

Hydrogenated amorphous silicon(a-Si:H) films which were deposited by plasma enhanced chemical deposition(PECVD) have been recrystallized by the two-step rapid thermal annealing(RTA) employing the halogen lamp. The a-Si:H films evolve hydrogen explosively during the high temperature crystallzation step. In result, the recrystallized polycrystalline silicon(poly-Si) films have poor surface morphology. In order to avoid the hydrogen evolution, the films have undergone the dehydrogenation step prior to the crystallization step Before the RTA process, the active area of thin film transistors (TFT's) was patterned. The prepatterning of the a-Si:H active islands may reduce thermal damage to the glass substrate during the recrystallization. The computer generated simulation shows the heat propagation from the a-Si:H islands into the glass substrate. We have fabricated the poly-Si TFT's on the silicon wafers. The maximun ON/OFF current ratio of the device was over $10^5$.