• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.878-881
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• 2009

As for the technology developed for network security, there is little difference of design ability between the domestic and the foreign studies. Although the development of 2048 RSA processor has been undergone, the processing speed does not meet the requirement due to its long width. These days, an RSA processor architecture with higher speed comsuming less resource is necessary. As for the development of RNG (Random Number Generator), the technology trend is moving from PRNG (Pseudo Random Number Generator) to TRNG (True Random Number Generator), also requiring less area and high speed.

• TTA Journal
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• s.80
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• pp.98-104
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• 2002

타원곡선 암호는 기존의 RSA나 Diffie-Hellman, DSA 등에 비해 짧은 키 길이를 사용하면서도 훨씬 빠른 구현이 가능하므로 다양한 국제 표준들에서 이를 지원하고자 하는 노력이 급증하고 있다. 본 기고에서는 타원곡선 암호와 관련된 국제표준들의 표준화 동향과 함께 현재 TTA 정보통신단체표준으로 제정된 국내 타원곡선 전자서명 표준인 EC-KCDSA에 대해서 간략히 소개하기로 한다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.4
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• pp.318-326
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• 2011

Public key cryptosystem applications are very difficult in Ubiquitos environments due to computational complexity, memory and power constrains. HECC offers the same of levels of security with much shorter bit-lengths than RSA or ECC. Scalar multiplication is the core operation in HECC. T.Lange proposed inverse free scalar multiplication on genus 2 HECC. However, further coordinate must be access to SCA and need more storage space. This paper developed secure scalar multiplication algorithm with simultaneous inversion algorithm in HECC. To improve the over all performance and security, the proposed algorithm adopt the comparable technique of the simultaneous inversion algorithm. The proposed algorithm is resistant to DPA and SPA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.7
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• pp.651-662
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• 1991

An improved modular multiplication algorithm for RSA type public key cryptosystem and its application to a serial communication cricuit are presented. Correction on a published fast modular multiplication algorithm is proposed and verified thru simulation. Cryptosystem for RS 232C communication protocol isdesigned and prototyped for low speed data exchange between computers. The system adops the correct algoroithm and operates successfully using a small size key.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.24-26
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• 2000

본 논문에서는 RSA 암호 시스템의 핵심 과정인 모듈로 멱승(Modular Exponentiation) 연산에 대한 새로운 하드웨어 구조를 제시한다. 기존의 몽고메리 알고리즘을 사용하였지만 다른 논문들이 Dependence Graph를 수직으로 매핑(Mapping)한 것과는 달리 여기서는 수평으로 매핑하여 1차원 선형 어레이(linear array) 구조를 구성하였다. 본 논문에서 사용한 방법의 장점은 결과가 시리얼(serial)로 나와서 바로 입력으로 들어갈 수 있기 때문에 100%의 처리율(throughput)을 이룰 수 있고, 수직 매핑 방식에 비해 절반의 클럭 횟수로 연산을 해낼 수 있다는 점이다. 또한 내부 계산 구조의 지역성(Locality) , 규칙성(Regularity) 및 모듈성(Modularity) 등으로 인해 실시간 고속 처리를 위한 VLSI 구현에 적합하다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.6
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• pp.563-570
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• 1987

In this paper a new RSA public-key cryptosystem which expands conventional RSA pubilc-key cryptosystem is suggested. The number of multiplication times is increased by expanding the modulus parameters p, q which are the foundation of ciphering. As a result tha amount of calculation which required in cryptoanalysis is increased, and we could improve strength of RSA public-key cryptography through a proof based on integral number theory.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1999.12a
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• pp.199-208
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• 1999

대부분의 암호이론은 공개되어 있기 때문에 정보보안 기술의 안전성은 암호 알고리즘과 키 길이에 의존성이 크다. 본 논문에서는 해쉬함수와 카오스 함수를 이용하여 암\ulcorner복호화를 위한 권장 키 길이보다 작은 길이의 일회성을 갖는 공개키와 비밀키를 생성하여 공개키 암호 알고리즘의 대표격인 RSA 암호방식에 적용하여 본다. 이러한 일회성 키를 사용함으로써 소인수 분해 알고리즘의 개선과 시스템의 발전에서 오는 증가된 키의 길이를 사용하는 경우보다 키의 길이가 길지 않으므로 스마트 카드와 같은 제한된 메모리에서 실용적으로 사용할 수 있을 뿐만 아니라, 암\ulcorner복호화를 수행하는 처리 시간을 단축 시칠 수 있으며, 키 관리면에서도 여러개의 공개키/비밀키를 사용하는 경우보다 실용적이다.

• Proceedings of the Korea Multimedia Society Conference
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• 2012.05a
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• pp.53-53
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• 2012

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.3C
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• pp.256-262
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• 2002

This paper presents a novel radix-4 modular multiplication algorithm based on the sign estimation technique (3). The sign estimation technique detects the sign of a number represented in the form of a carry-sum pair. It can be implemented with 5-bit carry look-ahead adder. The hardware speed of the cryptosystem is dependent on the performance modular multiplication of large numbers. Our algorithm requires only (n/2+3) clock cycle for n bit modulus in performing modular multiplication. Our algorithm out-performs existing algorithm in terms of required clock cycles by a half, It is efficient for modular exponentiation with large modulus used in RSA cryptosystem. Also, we use high-speed adder (7) instead of CPA (Carry Propagation Adder) for modular multiplication hardware performance in fecal stage of CSA (Carry Save Adder) output. We apply RL (Right-and-Left) binary method for modular exponentiation because the number of clock cycles required to complete the modular exponentiation takes n cycles. Thus, One 1024-bit RSA operation can be done after n(n/2+3) clock cycles.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.34-41
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• 2002

This paper describes a scalable implementation method of a word-based RSA cryptoprocessor using pseudo carry look-ahead adder The basic organization of the modular multiplier consists of two layers of carry-save adders (CSA) and a reduced carry generation and Propagation scheme called the pseudo carry look-ahead adder for the high-speed final addition. The proposed modular multiplier does not need complicated shift and alignment blocks to generate the next word at each clock cycle. Therefore, the proposed architecture reduces the hardware resources and speeds up the modular computation. We implemented a single-chip 1024-bit RSA cryptoprocessor based on the word-based modular multiplier with 256 datapaths in 0.5${\mu}{\textrm}{m}$ SOG technology after verifying the proposed architectures using FPGA with PCI bus.