• Title/Summary/Keyword: RS codes

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Efficient VLSI Architecture for Factorization in Soft-Decision Reed-Solomon List Decoding (연판정 Reed-Solomon 리스트 디코딩의 Factorization을 위한 효율적인 VLSI 구조)

  • Lee, Sung-Man;Park, Tae-Guen
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.11
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    • pp.54-64
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    • 2010
  • Reed-Solomon (RS) codes are the most widely used error correcting codes in digital communications and data storage. Recently, Sudan found algorithm of list decoder for RS codes. List decoder has larger decoding radius than conventional hard-decision decoding algorithms and return more than one candidate polynomial. But, the algorithm includes interpolation and factorization step that demand massive computations. In this paper, an efficient architecture and processing schedule are proposed. The architecture consists of R-MAC, memories, and control unit. The R-MAC computes both of RC and PU steps that are main part of the factorization algorithm. The proposed architecture can achieve higher hardware utilization efficiency (HUE) and throughput by using efficient processing schedule and memory architecture. Also, the architecture can be designed flexibly with scalability for various applications. We design and synthesize our architecture using Dongbu-Anam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 330MHz.

The Analysis about Channel Code Performance of Underwater Channel (수중통신채널에서 고려되는 채널 부호의 성능 분석)

  • Bae, Jong-Tae;Kim, Min-Hyuk;Choi, Suk-Soon;Jung, Ji-Won;Chun, Seung-Yong;Dho, Kyeong-Cheol
    • The Journal of the Acoustical Society of Korea
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    • v.27 no.6
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    • pp.286-295
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    • 2008
  • Underwater acoustic communication has multi path error because of reflection by sea-level and sea-bottom. The multipath of underwater channel causes signal distortion and error floor. In this paper, we consider the use of various channel coding schemes such as RS code, convolutional code, cross-layer code and LDPC code in order to compensate the multipath effect in underwater channel. As shown in simulation results, characteristic of multipath error is similar to that of random error, so interleaver has little effect for error correcting. For correcting of error floor by multipath error, it is necessary strong channel codes like LDPC code that is similar to Shannon's limit. And the performance of concatenated codes including RS codes has better performance than using singular channel codes.

An Efficient Recursive Cell Architecture for Modified Euclidean Algorithm to Decode Reed-Solomon Code (Reed-Solomon부호의 복호를 위한 수정 유클리드 알고리즘의 효율적인 반복 셀 구조)

  • Kim, Woo-Hyun;Lee, Sang-Seol;Song, Moon-Kyou
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.1
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    • pp.34-40
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    • 1999
  • Reed-Solomon(RS) codes have been employed to correct burst errors in applications such as CD-ROM, HDTV, ATM and digital VCRs. For the decoding RS codes, the Berlekamp-Massey algorithm, Euclidean algorithm and modified Euclidean algorithm(MEA) have been developed among which the MEA becomes the most popular decoding scheme. We propose an efficient recursive cell architecture suitable for the MEA. The advantages of the proposed scheme are twofold. First, The proposed architecture uses about 25% less clock cycles required in the MEA operation than[1]. Second, the number of recursive MEA cells can be reduced, when the number of clock cycles spent in the MEA operation is larger than code word length n. thereby buffer requirement for the received words can be reduced. For demonstration, the MEA circurity for (128,124) RS code have been described and the MEA operation is verified through VHDL.

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Adaptive-and-Resolvable Fractional Repetition Codes Based on Hypergraph

  • Tiantian Wang;Jing Wang;Haipeng Wang;Jie Meng;Chunlei Yu;Shuxia Wang
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.17 no.4
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    • pp.1182-1199
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    • 2023
  • Fractional repetition (FR) codes can achieve exact uncoded repair for multiple failed nodes, with lower computational complexity and bandwidth overhead, and effectively improve repair performance in distributed storage systems (DSS). The actual distributed storage system is dynamic, that is, the parameters such as node storage overhead and number of storage nodes will change randomly and dynamically. Considering that traditional FR codes cannot be flexibly applied to dynamic distributed storage systems, a new construction scheme of adaptive-and-resolvable FR codes based on hypergraph coloring is proposed in this paper. Specifically, the linear uniform regular hypergraph can be constructed based on the heuristic algorithm of hypergraph coloring proposed in this paper. Then edges and vertices in hypergraph correspond to nodes and coded packets of FR codes respectively, further, FR codes is constructed. According to hypergraph coloring, the FR codes can achieve rapid repair for multiple failed nodes. Further, FR codes based on hypergraph coloring can be generalized to heterogeneous distributed storage systems. Compared with Reed-Solomon (RS) codes, simple regenerating codes (SRC) and locally repairable codes (LRC), adaptive-and-resolvable FR codes have significant advantages over repair locality, repair bandwidth overhead, computational complexity and time overhead during repairing failed nodes.

Performance Analysis of Low Bit-Rate Image Transmission over Concatenated Code WLL system (연쇄 부호화된 WLL 시스템을 통한 저비트율 영상전송 성능분석)

  • 이병길;조현욱;박길흠
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.9B
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    • pp.1616-1623
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    • 1999
  • This paper describes error resilient coding scheme is added in WLL system and its application for robust low-bit rate still image transmission over power controlled W-CDA system Rayleigh fading channels. The baseline JPEG compressing methods are uses in image coding over wireless channel. The channel uses Reed-Solomon(RS) outer codes concatenated with convolutional inner codes, and truncated type I hybrid ARQ protocol based on the selective repeat strategy and the RS error detection capability. Simulation results are proved for the statistics of the frame-error bursts of the proposed system in comparison with conventional WLL system. it gains the 2 dB of the Eb/No in same BER.

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Reducing PAPR of OFDM Signals Using Modified Partial Transmit Sequences Technique Based on Erasure Decoding (소실 복호 기반의 수정된 PTS 기법을 이용한 OFDM 신호의 PAPR 감소)

  • Kong, Min-Han;Song, Moon-Kyou
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.8C
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    • pp.775-781
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    • 2007
  • In this paper, a modified PTS(Partial Transmit Sequences) technique that uses erasure decoding of RS (Reed-Solomon) codes is presented. At the transmitter, some check symbols in a RS codeword partitioned into subblocks are phase-rotated by phase factors. The receiver decodes received codewords by regarding the phase-rotated check symbols as erasures. Hence, this technique does not need to transmit the side information about the phase factors chosen at the transmitter. The complexity of the receiver is also reduced since the estimation process for the phase factors is not required in the receiver. There is no performance degradation due to the transmission error of the side information or the estimation error of the phase factors. To evaluate the performance of the proposed PTS technique, the CCDF(Complementary Cumulative Distribution Function) of PAPR and the BER(Bit Error Rate) are compared with those of the conventional PTS techniques.

Design of Reed Solomon Encoder/Decoder for Compact Disks (컴팩트 디스크를 위한 Reed Solomon 부호기/복호기 설계)

  • 김창훈;박성모
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.281-284
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    • 2000
  • This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk with double error detecting and correcting capability. A variety of error correction codes(ECCs) have been used in magnetic recordings, and optical recordings. Among the various types of ECCs, Reed Solomon(RS) codes has emerged as one the most important ones. The most complex circuit in the RS decoder is the part for finding the error location numbers by solving error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid's algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and peformed logic synthesis using the SYNOPSYS CAD tool. The total umber of gate is about 11,000 gates.

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A Study on a concatenated RS code and Turbo code for OFDM system over burst noise channel

  • Choi Sang Min;Moon Byung Hyun;Park Jong Soo
    • Proceedings of the IEEK Conference
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    • 2004.08c
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    • pp.649-652
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    • 2004
  • In this paper, a concatenated RS and Turbo code is proposed for OFDM system over burst error channel. The concatenated code used in this study is a RS(255,2D2) code and a rate 1/2 turbo code. The turbo code uses 2 recursive systematic convolutional (RSC) code as the constituent codes and the parity bit are punctured to get the desired code rate. It is shown by simulation that the conventional OFDM system fails when there exists burst noise. The concatenated RS and turbo code obtains at least 5dB gain over the turbo code at the bit error probability of $10^{-3}$.

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The Concatenated Coding Scheme for OFDM system over burst noise channel

  • Byung-Hyun, Moon;Sang-Min, Choi
    • Journal of Korea Society of Industrial Information Systems
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    • v.9 no.2
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    • pp.17-22
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    • 2004
  • In this paper, a concatenated RS and Turbo code is proposed for OFDM system over burst error channel. The concatenated code used in this study is a RS(255,202) code and a rate 1/2 turbo code. The turbo code uses 2 recursive systematic convolutional (RSC) code as the constituent codes and the parity bit are punctured to get the desired code rate. It is shown by simulation that the conventional OFDM system fails when there exists burst noise. The concatenated RS and turbo code obtains at least 5dB gain over the turbo code at the bit error probability of 10/sup -3/.

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A Study of PLC Simulation for Automobile Panel AS/RS (자동차 패널 자동창고 시스템의 PLC 시뮬레이션 적용 연구)

  • Ko, Min-Suk;Koo, Lock-Jo;Kwak, Jong-Geun;Hong, Sang-Hyun;Wang, Gi-Nam;Park, Sang-Chul
    • Journal of the Korea Society for Simulation
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    • v.18 no.3
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    • pp.1-11
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    • 2009
  • This paper illustrates a case study of PLC logic simulation in a car manufacturing system. It was developed to simulate and verify PLC control program for automobile panel AS/RS. Because car models become varied, the complexity of supply problem is increasing in the car manufacturing system. To cope with this problem, companies use the AS (automated storage) and RS (retrieval system) but it has logical complexity. Industrial automated process uses PLC code to control the AS/RS, however control information and control codes (PLC code) are difficult to understand. This paper suggests a PLC simulation environment, using 3D models and PLC code with realistic data. Data used in this simulation is based on realistic 3D model and I/O model, using actual size and PLC signals, respectively. The environment is similar to a real factory; users can verify and test the PLC code using this simulation before the implementation of AS/RS. Proposed simulation environment can be used for test run of AS/RS to reduce implementation time and cost.