• 제목/요약/키워드: Quantum circuit

검색결과 172건 처리시간 0.023초

다중 양자우물 주사형 다이오드와 펄스-모드 신경회로망 구현을 위한 그 응용 (A Novel Multi-Quantum Well Injection Mode Diode And Its Application for the Implementation of Pulse-Mode Neural Circuits)

  • Song Chung Kun
    • 전자공학회논문지A
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    • 제31A권8호
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    • pp.62-71
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    • 1994
  • A novel semiconductor device is proposed to be used as a processing element for the implementation of pulse-mode neural networks which consists of alternating n' GaAs quantum wells and undoped AlGaAs barriers sandwitched between n' GaAs cathode and P' GaAs anode and in simple circuit in conjunction with a parallel capacitive and resistive load the trigger circuit generates neuron-like pulse train output mimicking the function of axon hillock of biological neuron. It showed the sigmoidal relationship between the frequency of the pulse-train and the applied input DC voltage. In conjunction with MQWIMD the various neural circuits are proposed especially a neural chip monolithically integrated with photodetectors in order to perfrom the pattern recognition.

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RSFQ 논리회로의 개발과 회로설계에 대한 지연시간 고려 (Development of RSFQ Logic Circuits and Delay Time Considerations in Circuit Design)

  • 강준희;김진영
    • Progress in Superconductivity
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    • 제9권2호
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    • pp.157-161
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    • 2008
  • Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

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단자속 양자 NDRO 회로의 설계와 측정 (Design and Measurements of an RSFQ NDRO circuit)

  • 정구락;홍희송;박종혁;임해용;강준희;한택상
    • 한국초전도저온공학회:학술대회논문집
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    • 한국초전도저온공학회 2003년도 추계학술대회 논문집
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    • pp.76-78
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    • 2003
  • We have designed and tested an RSFQ (Rapid Single Flux Quantum) NDRO (Non Destructive Read Out) circuit for the development of a high speed superconducting ALU (Arithmetic Logic Unit). When designing the NDRO circuit, we used Julia, XIC and Lmeter for the circuit simulations and layouts. We obtained the simulation margins of larger than $\pm$25%. For the tests of NDRO operations, we attached the three DC/SFQ circuits and two SFQ/DC circuits to the NDRO circuit. In tests, we used an input frequency of 1 KHz to generate SFQ Pulses from DC/SFQ circuit. We measured the operation bias margin of NDRO to be $\pm$15%. The circuit was measured at the liquid helium temperature.

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ALU의 개발을 위한 RSFQ DFFC 회로의 설계 (RSFQ DFFC Circuit Design for Usage in developing ALU)

  • 남두우;김규태;강준희
    • 한국초전도저온공학회:학술대회논문집
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    • 한국초전도저온공학회 2003년도 추계학술대회 논문집
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    • pp.123-126
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    • 2003
  • RSFQ (Rapid Single Flux Quantum) circuits are used in many practical applications. RSFQ DFFC (Delay Flip-Flop with complementary outputs) circuits can be used in a RAM, an ALU (Arithmetic Logic Unit), a microprocessor, and many communication devices. A DFFC circuit has one input, one switch input, and two outputs (output l and output 2). DFFC circuit functions in such way that output 1 follows the input and output 2 is the complement of the input when the switch input is "0." However, when there is a switch input "1."the opposite output signals are generated. In this work, we have designed an RSFQ DFFC circuit based on 1 ㎄/$\textrm{cm}^2$ niobium trilayer technology. As circuit design tools, we used Xic, WRspice, and Lmeter After circuit optimization, we could obtain the bias current margins of the DFFC circuit to be above 32%.

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단자속 양자 AND gate의 시뮬레이션과 Layout (Simulation and Layout of Single Flux Quantum AND gate)

  • 정구락;박종혁;임해용;강준희;한택상
    • 한국초전도저온공학회:학술대회논문집
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    • 한국초전도저온공학회 2002년도 학술대회 논문집
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    • pp.141-143
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    • 2002
  • We have simulated and Laid out a Single Flux Quantum(SFQ) AND gate for Arithmetic Logic Unit by using XIC, WRspice and Lmeter. This circuit is a combination of two D Flip-Flop. D Flip- Flop and dc SQUID are the similar shape from the fact that it has the a loop inductor and two Josephson junction. We also obtained operating margins and accomplished layout of the AND gate. We got the margin of $\pm$42% over.

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RSFQ DFFC Circuit Design for Use in ALU

  • Nam, Doo-Woo;Kim, Kyu-Tae;Kang, Joon-Hee
    • 한국초전도학회:학술대회논문집
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    • 한국초전도학회 2003년도 High Temperature Superconductivity Vol.XIII
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    • pp.50-50
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    • 2003
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DC/SFQ 회로의 시뮬레이션 및 작동 (Simulation and Operation of DC/SFQ Circuit)

  • 박종혁;정구락;임해용;한택상;강준희
    • 한국초전도저온공학회:학술대회논문집
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    • 한국초전도저온공학회 2002년도 학술대회 논문집
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    • pp.109-110
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    • 2002
  • The purpose of a superconductive DC/SFQ circuit is to produce a controlled number of picosecond single flux quantum pulses at the output when a slowly changing DC current is applied to the input. In this work, we have designed and simulated a DC/SFQ circuit based on Nb/Al$O_{x}$/Nb Josephson junction technology. From the simulation, we could obtain the margins for various circuit parameters. And also we have successfully operated a DC/SFQ circuit which was fabricated with the same design. The margin for the input bias current of the circuit was observed to be of $\pm$60%, which was very close to the simulated value.

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셀 간 상호작용을 이용한 XOR 게이트 기반의 양자점 셀룰러 오토마타 T 플립플롭 (XOR Gate Based Quantum-Dot Cellular Automata T Flip-flop Using Cell Interaction)

  • 유찬영;전준철
    • 문화기술의 융합
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    • 제7권1호
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    • pp.558-563
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    • 2021
  • 양자점 셀룰라 오토마타(Quantum-Dot Cellular Automata)는 기존의 CMOS 회로의 물리적 크기 한계를 극복하여 효율적인 회로 설계가 가능할 뿐만 아니라 에너지 효율이 우수한 특징 때문에 많은 연구 단체에서 주목받고 있는 차세대 나노 회로 설계기술이다. 본 논문에서는 QCA를 이용하여 기존 디지털 회로 중 하나인 T 플립플롭 회로를 제안한다. 기존에 제안되었던 T 플립플롭들은 다수결게이트를 기반으로 설계되었기 때문에 회로가 복잡하며 지연시간이 길다. 따라서 다수결게이트를 최소화시키며, 셀 간 상호작용을 이용한 XOR 게이트 기반의 T 플립플롭을 설계함으로써 회로의 복잡도를 줄이고, 지연시간을 최소화한다. 제안하는 회로는 QCADesigner를 사용하여 시뮬레이션을 진행하며, 기존에 제안된 회로들과 성능을 비교 및 분석한다.

Size-dependent Optical and Electrical Properties of PbS Quantum Dots

  • Choi, Hye-Kyoung;Kim, Jun-Kwan;Song, Jung-Hoon;Jeong, So-Hee
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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    • pp.186-186
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    • 2012
  • This report investigates a new synthetic route and the size-dependent optical and electrical properties of PbS nanocrystal quantum dots (NQDs) in diameters ranging between 1.5 and 6 nm. Particularly we synthesize ultra-small sized PbS NQDs having extreme quantum confinement with 1.5~2.9 nm in diameter (2.58~1.5 eV in first exciton energy) for the first time by adjusting growth temperature and growth time. In this region, the Stokes shift increases as decreasing size, which is testimony to the highly quantum confinement effect of ultra-small sized PbS NQDs. To find out the electrical properties, we fabricate self-assembled films of PbS NQDs using layer by layer (LBL) spin-coating method and replacing the original ligands with oleic acid to short ligands with 1, 2-ethandithiol (EDT) in the course. The use of capping ligands (EDT) allows us to achieve effective electrical transport in the arrays of solution processed PbS NQDs. These high-quality films apply to Schottky solar cell made in an glass/ITO/PbS/LiF/Al structure and thin-film transistor varying the PbS NQDs diameter 1.5~6 nm. We achieve the highest open-circuit voltage (<0.6 V) in Schottky solar cell ever using PbS NQDs with first exciton energy 2.58 eV.

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확장성을 고려한 QCA BCD-3초과 코드 변환기 설계 (Design of Extendable BCD-EXCESS 3 Code Convertor Using Quantum-Dot Cellular Automata)

  • 유영원;전준철
    • 한국항행학회논문지
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    • 제20권1호
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    • pp.65-71
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    • 2016
  • 양자점 셀룰라 오토마타 (QCA; quantum-dot cellular automata)는 나노 규모의 크기와 낮은 전력 소비로 각광받고 있으며, CMOS 기술의 규모의 한계를 극복할 수 있는 대체 기술로 떠오르고 있다. 현재까지 QCA상에서 설계된 BCD-3초과 코드는 확장성을 고려하지 않았으며 대규모 회로 설계에는 적합하지 않았다. 이를 해결하기 위해 본 논문에서는 확장성을 고려한 BCD-3초과 코드 회로를 설계한다. 확장이 가능한 구조를 설계하기 위해 확장된 교차부 구조를 이용하여 입력과 출력의 흐름을 제어하고, 출력되는 값들의 동기화를 위해 5입력 다수결 게이트를 이용한다. 설계한 구조에 대해 QCADesigner를 이용하여 시뮬레이션을 수행한 후 그 결과에 대해 유효성을 검증한다. 제안된 구조는 기존의 URG BCD-3초과 코드변환기와 비교하여 32개의 게이트를 줄이며 빈 공간의 비율 또한 7% 감소시켰다. 또한 확장성이 고려되지 않은 기존의 QCA BCD-3초과 코드 변환기가 회로 확장 시 필요한 7개의 클럭을 1개의 클럭으로 줄였다.