• Journal of IKEEE
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• v.18 no.4
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• pp.612-619
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• 2014

This paper proposes a real-time multi-camera video surveillance system with automatic resolution control using motion detection. In ordinary times, it acquires 4 channels of QVGA images, and it merges them into single VGA image and transmit it. When motion is detected, it automatically increases the resolution of motion-occurring channel to VGA and decreases those of 3 other channels to QQVGA, and then these images are overlaid and transmitted. Thus, it can magnifies and watches the motion-occurring channel while maintaining transmission bandwidth and monitoring all other channels. When it is synthesized with 0.18 um technology, the maximum operating frequency is 110 MHz, which can theoretically support 4 HD cameras.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.20-27
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• 2011

A CMOS Image Sensor(CIS) mounted on mobile appliances always needs a low power consumption because of the battery life cycle. In this paper, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination, a low power single slope A/D converter with a novel comparator, and etc. Based on 0.13um CMOS process, the chip satisfies QVGA resolution($320{\times}240$ pixels) whose pitch is 2.25um and whose structure is 4-Tr active pixel sensor. From the experimental results, the ADC in the middle of CIS has a 10-b resolution, the operating speed of CIS is 16 frame/s, and the power dissipation is 25mW at 3.3V(Analog)/1.8V(Digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption is reduced approximately by 22% in sleep mode, 20% in operating mode.

• Journal of the Korea Society of Computer and Information
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• v.20 no.1
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• pp.1-10
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• 2015

In this paper, we propose an efficient parallel implementation method of a widely used complex four-stage fire detection algorithm using a graphics processing unit (GPU) to improve the performance of the algorithm and analyze the performance of the parallel implementation method. In addition, we use seven different resolution videos (QVGA, VGA, SVGA, XGA, SXGA+, UXGA, QXGA) as inputs of the four-stage fire detection algorithm. Moreover, we compare the performance of the GPU-based approach with that of the CPU implementation for each different resolution video. Experimental results using five different fire videos with seven different resolutions indicate that the execution time of the proposed GPU implementation outperforms that of the CPU implementation in terms of execution time and takes a 25.11ms per frame for the UXGA resolution video, satisfying real-time processing (30 frames per second, 30fps) of the fire detection algorithm.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1001-1004
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• 2008

An advanced backplane circuit technology for AMOLED using amorphous silicon TFTs with commercial level reliability, uniformity and lifetime was recently integrated into a prototype device. Differential aging of T98>100 hrs at 200 cd/m2 brightness and >10,000hrs lifetime is demonstrated. A 2.2" QVGA ($240{\times}320$) prototype has been developed and shown having the above-mentioned high performance.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1033-1034
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• 2005

High resolution 2.1” QVGA LTPS LCD (190ppi) having high aperture ratio of 65% could be successfully developed using state-of-the-art SLS technology and active/gate storage structure. Cost effective P-MOS 6-Mask structure was used. Full gate and transmission gate circuits are integrated in the panel. The high aperture ratio was obtained by using active/gate capacitance structure, which can reduce storage capacitance area. The aperture ratio was increased to 65% from 49% of conventional gate/data capacitance structure. The brightness was increased from 180cd to 270cd without any degradation of optical properties such as contrast ratio, flicker or crosstalk.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.40-47
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• 2009

In this paper, we present the design of a source driver of QVGA scale TFT-LCD driver IC which uses a mixed driving method and performs $\gamma$-correction to improve image. The source driver with 240 RGB ${\times}$ 320 dots resolution drives a TFT-LCD panel through 720 channels and implements 262k colors using 18-bit RGB data format. The mixed driving method is a mixture the channel amp. driving method with high drivability and the gray amp. driving method with small area, which remarkably reduces channel driver areas. The driver has been designed using the $0.35{\mu}m$ Magnachip embedded DRAM technology and simulated using the HSPICE simulator. The results show that our source driver operates well with y-correction and the channel driver has $17{\mu}s$ channel driving time with only 78 driving amplifiers and control logic.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.64-69
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• 2013

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two-step single-slope A/D converter is proposed. The A/D converter is composed of both a 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D converter. In order to have a small noise characteristics, further, a Digital Correlated Double Sampling(D-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35mW at 3.3V supply voltage. The measured conversion speed is 10us, and the frame rate is 220 frames/s.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.104-110
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• 2011

A CMOS Image Sensor (CIS) mounted on mobile appliances requires low power consumption due to limitations of the battery life cycle. In order to reduce the power consumption of CIS, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination and a low power single slope analog-to-digital (A/D) converter with a sleep-mode comparator. Based on 0.13 ${\mu}m$ CMOS process, the chip satisfies QVGA resolution (320 ${\times}$ 240 pixels) that the cell pitch is 2.25 um and the structure is a 4-Tr active pixel sensor. From the experimental results, the performance of the CIS has a 10-b resolution, the operating speed of the CIS is 16 frame/s, and the power dissipation is 25 mW at a 3.3 V(analog)/1.8 V(digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption was reduced by approximately 22% in the sleep mode, and 20% in the active mode.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.395-398
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• 2004

We developed an a-Si TFT-LCD panel with integrated gate driver circuit using a standard 5-MASK process. To minimize the effect of the a-Si TFT current and LC's capacitance variation with temperature, we developed a new a-Si TFT circuit structure and minimized coupling capacitance by changing vertical architecture above gate driver circuit. Integration of gate driver circuit on glass substrate enables single chip and 3-side free panel structure in a-Si TFT-LCD of QVGA(240$^{\ast}$320) resolution. And using double ASG structure the dead space of TFT-LCD panel could be further decreased.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.246-251
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• 2014

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA ($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.