• Title/Summary/Keyword: QP assignment

Search Result 4, Processing Time 0.017 seconds

Efficient QP-per-frame Assignment Method for Low-delay HEVC Encoder (저지연 HEVC 부호화기를 위한 효율적인 프레임별 양자화 파라미터 할당 방법)

  • Park, Sang-hyo;Jang, Euee S.
    • Journal of Broadcast Engineering
    • /
    • v.21 no.3
    • /
    • pp.349-356
    • /
    • 2016
  • In this paper, we propose an efficient assignment method that assigns quantization parameter (QP) in accordance with group of picture (GOP) structure given in HEVC encoder. Each video frames can have difference QP values based on given GOP configuration for HEVC encoding. Particularly, for important frames we can assign low QP values, and vice versa. However, there has not been thorough investigation on efficient QP assignment method by far. Even in HEVC reference software encoder, only monotonic QP assignment method is employed. Thus, the proposed method assign adaptive QP values to each GOP so that temporal dynamic activity between GOPs can be exploited. Through the experiment, the proposed method showed a 7.3% gain of compression performance in terms of BD-rate compared to HEVC test model (HM) in low-delay configuration, and outperformed the existing QP assignment study on average.

HEVC based Perceptual Video Coding using JND based Bit Assignment toward Perceptual Quality Enhancement (JND 기반 인지품질 향상 지향 비트 할당 방법 및 이를 이용한 HEVC 기반 인지 비디오 부호화)

  • Kim, Dae Eun;Kim, Munchurl
    • Proceedings of the Korean Society of Broadcast Engineers Conference
    • /
    • 2014.06a
    • /
    • pp.203-205
    • /
    • 2014
  • 본 논문에서는 HEVC 기반 비디오 부호화에 있어 CTU 단위의 시각 민감도에 따라 CTU 별로 QP 를 조절하여 주관적 화질을 향상시키는 방법을 제안한다. 시각 민감도를 측정하는 방법으로서 화소 영역에서의 최소가지차(JND, just noticeable distortion)를 계산하여 이용하였고, 이를 HM 12.0 참조 소프트웨어에서 이용되는 $R-{\lambda}$ 모델 기반의 율 제어 모듈에 결합하여 시각 민감도에 따라 QP 를 제어할 수 있도록 하였다. 시각 민감도가 큰 영상의 영역에 대해서는 상대적으로 작은 QP 값을, 시각민감도가 작은 영역에 대해서는 큰 QP 값을 양자화 과정에 적용함으로써, 시각 민감도가 작은 영역에 대해서는 사용 비트양을 절약하고, 절약된 비트를 상대적으로 시각 민감도가 큰 영역을 위해 사용함으로써 비디오의 주관적 화질을 향상시킬 수 있었다. 뿐만 아니라 이를 하드웨어에 적용 가능하게 하기 위해 HM 12.0 기반 하드웨어 구현을 위한 소프트웨어 플랫폼에 구현하여 실험한 결과, $R-{\lambda}$ 모델 율 제어 알고리즘으로 율 제어 하여 부호화 한 경우 Y-PSPNR(peak signal to perceptual noise ratio)에 대한 BD-rate 는 평균 9.4%의 이득이 있었음을 확인하였다.

  • PDF

고삼투압이 재조합 Erythropoietin의 생산과 당쇄구조에 미치는 효과

  • Jeong, Yeon-Tae;Kim, Jeong-Hoe
    • 한국생물공학회:학술대회논문집
    • /
    • 2001.11a
    • /
    • pp.221-224
    • /
    • 2001
  • Effect of hyperosmotic pressure on growth of recombinant Chinese hamster 。 vary cells and Erythropoietin (EPO) production was investigated. Cells were cultivated in batch modes at various osmolalities. When the osmolality increased from 314 to 463mOsm/Kg, specific EPO productivity (qp) was increased up to 1.6-fold but cell growth was inhibited. EPO has a complex oligosaccharide structure that plays an important role in biological activity in vivo. To investigate the influence of hypoerosmotic pressure on the glycosylation, structural analysis of oligosaccharide was calTied out. Recombinant human EPO was produced by CHO cells grown under various osmotic pressure and purified from culture supernatants by heparin-sepharose affinity column and immunoaffinity column. N-linked oligosaccharides were released enzymatically and isolated by paper chromatography. The isolated oligosaccharides were labeled with fluorescent dye, 2-aminobenzamide and analyzed with MonoQ anion exchange chromatography and GlycosepN amide chromatography for the assignment of GU (glucose unit) value. Glycan analysis by HPLC showed that neutral (asialo) oligosaccharide was increased slightly with an increase in osmolality. In portion of sialylated glycan, total relative amount of mono- and di-sialyated glycan was increased but that of tri- and tetra-sialylated glycan decreased as osmolality was increased.

  • PDF

An Implementation of Multiple Access Memory System for High Speed Image Processing (고속 영상처리를 위한 다중접근 기억장치의 구현)

  • 김길윤;이형규;박종원
    • Journal of the Korean Institute of Telematics and Electronics B
    • /
    • v.29B no.10
    • /
    • pp.10-18
    • /
    • 1992
  • This paper considers and implementation of the memory system which provides simultaneous access to pq image points of block(p$\times$q), horizontal vector(1$\times$pq)and/vertical vector(pq$\times$1) in 2-dimension image array, where p and q are design parameters. This memory system consists of an address calculation circuit, address routing circuit, data routing circuit, module selection circuit and m memory modules where m>qp. The address calculation circuit computes pq addresses in parallel by using the difference of addresses among image points. Extra module assignment circuit is not used by improving module selection circuit with routhing circuit. By using Verilog-XL logic simulator, we verify the correctness of the memory system and estimate the performance. The implemented system provides simultaneous access to 16 image points and is 6 times faster than conventional memory system.

  • PDF