• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.3
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• pp.126-132
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• 1996

In this paper, the complexity reduction method for QCELP speech coder (IS-96) without any perfomrance degradation is proposed for the vecoder of CDMA digital cellular system. The energy terms in pitch parameter search and codebook search routines that require large computations are calculated recursively by utilizing the overlapped structure of code vectors in adaptive codebook and excitation codebook. The additional complexity reduction in the codebook search routine can be achieved by using a simple form in calculation of the energy term when the initial codebook value is zero. In the case of lower transmission rates such as 4,2,1 kbps, the complexity reduction by recursive calulations of energy term is increased.

• The Journal of the Acoustical Society of Korea
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• v.16 no.3E
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• pp.3-6
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• 1997

This paper reports on the optimal design of the excitation codebook in the 13 kbps variable rate QCELP coder of Korean speech. We present two optimal excitation codebooks which consist of 128 and 556 samples, respectively. For the design and test of the improved codebook, a data base of Korean speech is used. A quasi-Newton optimization algorithm was developed to design the codebook. The optimized codebook which remains sparse, can produce an average gain of 0.84 and 0.45 dB in SNR and SEGSNR respectively. Informal listening tests confirm the improvement in speech quality.

• Proceedings of the Acoustical Society of Korea Conference
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• 1995.06a
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• pp.137-140
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• 1995

In the paper, CDMA's vocoder algorithm, QCELP, was analyzed. And, 16-bit programmable DSP core for QCELP was designed. When it is used two MACs in DSP, we can implement low-power DSP and estimate decrease of parameter computation speed. Also, we implemented in FIFO memory using register file to increase the access time of the data. This DSP was designed using logic synthesis tool, COMPASS, by top-down design methodology. Therefore, it is possible to cope with rapid change at mobile communication market.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.1
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• pp.77-83
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• 1997

In this paper, we present a comparison between QCELP(Qualcomm Code Excited Linear Predictor) speech coder that is operating in digital mobile communication system and CS-ACELP(Conjugate Structure Algebraic Code Excited Linear Prediction) speech coder that is scheduled to use for IMT-2000 (International Mobile Telecommunications 2000) system. The performance comparison might give help to design of the speech coding algorithms so that the robustness of the algorithms to channel errors engaged by mobile communication system be optimized.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.172-179
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• 1996

In the paper, QCELP (qualcomm code excited linear predictive), CDMA (code division multiple access)'s vocoder algorithm, was analyzed. And then, a ptich parameter seaarch architecture for 16-bit programmable DSP(digital signal processor) for QCELP was designed. Because we speed up the parameter search through high speed DSP using two MACs, we can satisfy speech codec specifiction for the digital celluar. Also, we implemented in FIFO(first-in first-out) memory using register file to increase the access time of data. This DSP was designed using COMPASS, ASIC design tool, by top-down design methodology. Therefore, it is possible to cope with rapid change at mobile communication market.

• The Journal of the Acoustical Society of Korea
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• v.18 no.7
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• pp.33-38
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• 1999

In this paper, we combine a generalized analysis-by-synthesis (AbS) structure and an algebraic excitation scheme to propose a new 4kb/s speech codec. This codec partly uses the structure of G.729. We design a line spectrum pair (LSP) quantizer, an adaptive codebook, and an excitation codebook to fit the 4 kb/s bit rate. The codec has a 25㎳ algorithmic delay, which corresponds to a 20㎳ frame size and a 5㎳ lookahead. At the bit rates below 4kb/s, most CELP speech codecs using the AbS principle have a drawback that results a rapid degradation of speech quality. To overcome this drawback we use the generalized AbS structure which is efficient for the low bit rate speech codec. LP coefficients are converted to LSP and quantized using a predictive 2-stage VQ. A low complexity algebraic codebook which uses shifting method is used for the fixed codebook excitation, and gains of the adaptive codebook and the fixed codebook are quantized using the VQ. To evaluate the performance of the proposed codec A-B preference tests are done with the fixed rate 8kb/s QCELP. As the result of the test, the performance of the codec is similar to that of the fixed rate 8kb/s QCELP.

• The Journal of the Acoustical Society of Korea
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• v.24 no.7
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• pp.416-422
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• 2005

Speech recognition in digital communication systems has very low performance due to the spectral distortion caused by speech codecs. In this paper, the spectral distortion by speech codecs is analyzed and a pre-processing method which compensates for the spectral distortion is proposed for performance enhancement of speech recognition. Three standard speech codecs. IS-127 EVRC. ITU G.729 CS-ACELP and IS-96 QCELP. are considered for algorithm development and evaluation, and a single method which can be applied commonly to all codecs is developed. The performance of the proposed method is evaluated for three codecs, and by using the speech features extracted from the compensated spectrum. the recognition rate is improved by the maximum of $15.6\%$ compared with that using the degraded speech features.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06e
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• pp.293-296
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• 1998

본 논문에서는 다양한 멀티미디어 서비스를 위해 가변율 half rate 음성 부호화기를 설계하였다. 유, 무성음과 묵음의 구분을 위해 본 논문에서는 프레임 에너지와 음성 파라메터들을 이용한 효과적인 voicing 결정 알고리즘을 사용하였다. 유성음을 위한 half rate 음성 부호화기는 저속에서 좋은 특성을 보이는 generalized AbS구조를 이용하였다. LPC 계수는 LSP 계수로 변환한 후 predictive 2-stage VQ를 통해서 양자화하며, 여기 신호는 음질저하를 최소화하며 복잡도를 감소시킨 shift 방식의 대수적 고정 코드북 구조를 사용하고, 적응코드북과 여기코드북의 이득은 VQ로 양자화 하였다. 무성음을 위한 부호화기는 대부분이 유성음을 위한 부호화기와 동일하지만, 무성음에서는 피치간 상관도가 매우 낮으므로 피치 보간 방법을 사용하지 않고 개루프로 피치 lag를 찾은 후 전체 프레임에 사용한다. 1 kb/s 부호화기는 묵음 구간과 주변소음 구간에 사용되며 이 구간의 신호를 피치 성분이 미약한 주변소음들로 제한하고 이에 최적인 부음성 부호화기를 설계하였다. 최종적으로 완성된 가변율 half rate 부호화기는 voice activity factor(VAF)가 0.47인 시험음성에서 약 2.6 kb/s의 평균 전송률을 보였다. 주관적 음질 평가의 일환으로 IS-96 표준 코덱인 가변율 8 kb/s QCELP와 A-B preference 시험을 실시하였다. 시험 결과 평균전송률이 약 2배인 가변율 8 kb/s QCELP 보다 우수한 음질 성능을 보였다.

• ETRI Journal
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• v.19 no.3
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.1-13
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• 1999

As the complexity of DSP (Digital Signal Processing) applications increases, the need for new architectures supporting efficient high-level language compilers also grows. By combining several DSP processor specific features, such as single cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping, with a RISC core having many general purpose registers and orthogonal instructions, a high-performance and compiler-friendly RISC-based DSP processors can be designed. In this study, we develop a code-converter that can exploit these DSP architectural features by post-processing compiler-generated assembly code, and evaluate the performance effects of each feature using seven DSP-kernel benchmarks and a QCELP vocoder program. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.