• Proceedings of the KIEE Conference
• /
• 1998.11c
• /
• pp.981-983
• /
• 1998

In this paper, we present theoretical designs for a beam steering phased array antenna that uses a true time delay optical feeder. A variable true time delay is achieved by employing one tunable laser source and high dispersion fibers with different length. The wavelength tunable optical carrier propagation in a high-dipersion fiber realizes a true time delay, with the steering direction set by a single voltage controlling the wavelength. Beamsteering of a phased array antenna is obtained by controlling the tunable laser source. An employment of a high dispersion fiber response shows wide-band operation of beem steering antenna system.

• Journal of the Korean Society for Aviation and Aeronautics
• /
• v.21 no.1
• /
• pp.15-22
• /
• 2013

In oceanic flight routes, HF radio and satellite data links have weather restrictions, long propagation delay and low data throughput. In this paper, we propose oceanic aeronautical communications scheme in the VHF band based on ad-hoc communication. The proposed scheme organizes autonomously a multi-hop network that is divided into multiple local network using aircraft to fly long-distance communication and supports a hybrid type of multiple access, which consists of random access and TDMA (Time Division Multiple Access) scheme. In addition, several algorithms to apply spatial reuse of transmission to multi-hop long range communication environments have been proposed. The proposed system proves performance improvement on delay time as an effective solution to communicate end-to-end on the oceanic flight routes and strengthens the reliability of oceanic aeronautical communication.

• Journal of Institute of Control, Robotics and Systems
• /
• v.1 no.1
• /
• pp.38-42
• /
• 1995

This paper presents a target scoring method using shock wave signals, which are generated from the supersonic speed of a projectile. The shock wave is detected from three acoustic sensors located in the target plane and the difference of the delay times are measured. The target coordinates are calculated from the effective propagation of velocity (EPV) and the delay times of the shock wave; and the EPV is from the projectile velocity and the delay time. With a comparison between the measurement result and the known coordinates, the accuracy and the usefulness of the proposed scheme is validated.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.14 no.6
• /
• pp.1166-1170
• /
• 2011

For developing the ignition device for the interceptor of Korean active protection system, the design parameters of the ignition device which should have a short ignition delay time and sufficient energy for propellant ignition were studied. The electric primer instead of mechanical primer was adopted for deceasing delay time, and ignition code was used for decreasing the time difference of flame propagation from the flame holes. The developed ignition device showed the ignition delay time of a few ms. When the designed ignition device was applied to the open-type propulsion devices, the stable interior ballistic characteristic was showed in a firing test.

• 제어로봇시스템학회:학술대회논문집
• /
• 2001.10a
• /
• pp.58-58
• /
• 2001

This paper shows a practical approach that is robust to the errors causing path-delay in mobile wireless location, and analyzes its performance by comparing with other methods. NLOS(non-line-of-sight) error and multipath are two big sources of positioning error in wireless location. Contrary to GPS(global positioning system), they result from the terrestrial propagation of a signal. Especially, since LOS(line-of-sight) path between a transceiver and a receiver is blocked by intermediate buildings and topography, NLOS causes a signal to be reflected and diffracted. This path-delay error is very localized, and so, it is not easy to be estimated and mitigated. To treat such localized error, therefore ...

• The Journal of the Korea institute of electronic communication sciences
• /
• v.17 no.2
• /
• pp.351-356
• /
• 2022

The parity function can be implemented with XOR (exclusive-OR) and XNOR (exclusive NOR) circuit. In this paper we propose a high performance XOR-XNOR circuit. The proposed circuitreduced the internal load capacitance on critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit presents the improved characteristics in average propagation delay time, power dissipation, power-delay product (PDP), and energy-delay-product (EDP). The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit realizes the expected logic functions and achieves a reasonable performance.

• Journal of Information Processing Systems
• /
• v.20 no.1
• /
• pp.131-147
• /
• 2024

A routing strategy based on traffic prediction and dynamic cache allocation for satellite nodes is proposed to address the issues of high propagation delay and overall delay of inter-satellite and satellite-to-ground links in low Earth orbit (LEO) satellite systems. The spatial and temporal correlations of satellite network traffic were analyzed, and the relevant traffic through the target satellite was extracted as raw input for traffic prediction. An improved gradient boosting regression tree algorithm was used for traffic prediction. Based on the traffic prediction results, a dynamic cache allocation routing strategy is proposed. The satellite nodes periodically monitor the traffic load on inter-satellite links (ISLs) and dynamically allocate cache resources for each ISL with neighboring nodes. Simulation results demonstrate that the proposed routing strategy effectively reduces packet loss rate and average end-to-end delay and improves the distribution of services across the entire network.

• Proceedings of the IEEK Conference
• /
• 2002.07a
• /
• pp.349-352
• /
• 2002

This paper describes a design of a 1bit Carry Propagate Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1bit CPFA/S is compared with that of the CMOS 1bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/23 as low as that of the CMOS circuits. The transistors count, propagation-delay tittle and energy dissipation of the ADCL 4bit CPFA/S are compared with those of the ADCL 4bit Carry Propagate Adder/Subtracter (CPA/S). The transistors count and propagation-delay tittle are found to be reduced by 7.02% and 57.1%, respectively. Also, energy dissipation is found to be reduced by 78.4%. Circuit operation and performance are evaluated using a chain of the ADCL 1bit CPFA/S fabricated in a $1.21mutextrm{m}$ CMOS process. The experimental results show that addition and subtraction are operated with clock frequencies up to about 1㎒.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.11
• /
• pp.41-48
• /
• 2005

The crosstalk effects that can be observed in the very dee submicron semiconductor chips are due to the coupling capacitances between interconnect lines. The accuracy of the full-chip timing analysis is determined by the accuracy of the estimated propagation delays of cells and interconnects within the chip. This paper presents a CMOS cell driver model and delay calculation algerian capturing the crosstalk effects due to the coupling capacitances. The proposed model and algorithm were implemented in a delay calculation program and used to estimate the propagation delays of the benchmark circuits extracted from a chip layout. We observed that the average discrepancy from HSPICE simulation results is within $1\%$ for the circuits with a victim affected by $0\~10$ aggressors.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.18 no.4
• /
• pp.34-42
• /
• 1981

A 512-bit Task Programmable ROM has been designed and fabricated using PMOS technology. The content of the memory was written through the gate pattern during the fabrication process, and was checked by displaying the output of the chip on an oscilloscope with 512(32$\times$16) matrix points. The operation of the chip was surcessful with operating voltage from -6V to -l2V, The power consumption and propagation delay time have been measured to be 3mW and 13 $\mu$sec, respectively at -6 Volt. The power consunption increased to 27mW and propagation delay time decreased to 3$\mu$sec at -12V. The output of the chip was capable of driving the input of a TTL gate directly and retained a high impedence state when the chip solect function disabled the output.