• Journal of KIISE:Computer Systems and Theory
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• v.35 no.6
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• pp.284-292
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• 2008

The density of Memory has been increased by great challenge for memory technology; therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip(SoC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. We present a ARM processor-programmable built-in self-test(BIST) scheme suitable for embedded memory testing in the SoC environment. The proposed BIST circuit can be programmed vis an on-chip microprocessor.

• Journal of the Korean Society for information Management
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• v.20 no.4 s.50
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• pp.91-111
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• 2003

This paper shows that digital libraries can be understood through STIN models which emphasize interactions among components in networks. The enrollment strategies in the American Memory make human and non-human factors interact. Specifically, this paper articulates that the relationships between users and collections, between users and staff, and between users and users are closely linked through the strategies . Observing the linkages among these components ,this paper found that the enrollment processes not only draw users to the American Memory, but also alter roles of components and creates new roles and players for them. The alterations of roles and the resulting changes of relationships among components mean that digital libraries lead to transform the grounding of knowledge works in a society.

• The Korean Journal of Applied Statistics
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• v.26 no.1
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• pp.163-185
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• 2013

In this paper, we investigate the need to employ long-memory volatility models in terms of Value-at-Risk(VaR) estimation. We estimate the VaR of the KOSPI returns using long-memory volatility models such as FIGARCH and FIEGARCH; in addition, via back-testing we compare the performance of the obtained VaR with short memory processes such as GARCH and EGARCH. Back-testing says that there exists a long-memory property in the volatility process of KOSPI returns and that it is essential to employ long-memory volatility models for the right estimation of VaR.

• Journal of the Korean Society for Heat Treatment
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• v.7 no.2
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• pp.118-128
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• 1994

Five alloys were selected randomly in the composition range showing the best shape memory effect in Fe-Mn-Si system reported by Murakami. The shape memory effects of those alloys were mainly investigated through the training treatment which consisted of the repetition of 2% tensile deformation at room temperature and subsequent annealing at $600^{\circ}C$ above $A_r$ temperature. At the same deformation degress in rolling $600^{\circ}C$-annealing for 1 hr. showed the best shape memory effect, and 10%-deformation degrees represented maxima of the shpae memory effects at all annealing temperatures, $500^{\circ}C$, $600^{\circ}C$ and $700^{\circ}C$. The shape memory effects of the alloys were increased by increasing training cycle up to 5 cycles. This was because a large number of dislocations introduced by training process gave rise to increase in the austenite yield stress, and acted as nucleation sites for stress induced ${\varepsilon}$ martensite. The thermal cycling treatment, repetition of cooling in nitrogen at $-196{\circ}C$ and heating to $300^{\circ}C$ for 5 min., did not improve the shape memory effect.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.35-35
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• 2009

Capacitorless one transistor dynamic random access memory (1T-DRAM) cells were fabricated on the fully depleted strained-silicon-on-insulator (FD sSOI) and the effects of silicon back interface state on buried oxide (BOX) layer on the memory properties were evaluated. As a result, the fabricated 1T-DRAM cells showed superior electrical characteristics and a large sensing current margin (${\Delta}I_s$) between "1" state and "0" state. The back interface of SOI based capacitorless 1T-DRAM memory cell plays an important role on the memory performance. As the back interface properties were degraded by increase rapid thermal annealing (RTA) process, the performance of 1T-DRAM was also degraded. On the other hand, the properties of back interface and the performance of 1T-DRAM were considerably improved by post RTA annealing process at $450^{\circ}C$ for 30 min in a 2% $H_2/N_2$ ambient.

• The KIPS Transactions:PartA
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• v.11A no.7 s.91
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• pp.475-482
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• 2004

We live in the flood of information due to advancement of information communication and increase of E-mail. Managing users huge in-formation systematically and speedy searching are needed in these social advancement. In this thesis, in order to satisfy these requirement, We suggested Real-time LDAP Interface using Main Memory Resident Database Management System which can manage a lot of information fast systematically. It is expected that system can provide advantage of performance improvement through replacing Main Memory Resident Database Management System without change of application which is required high speed process.

• IE interfaces
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• v.18 no.2
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• pp.178-183
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• 2005

In this study, changes in memory performance, blood oxygen saturation and heart rate according to 30% concentration oxygen supply were observed. Ten healthy male and female college students (male:$25.8{\pm}0.8$ years, female: $24.2{\pm}1.9$ years) participated in the study. The experiment was performed as Rest (1min.), Control task (1min.), Word presentation (1min.), Reaction time task (1min.), Distractor (2min.), and Word recall (1min.) and the physiological signals such as blood oxygen saturation and heart rate were measured throughout the stages. Subjects who received 30% oxygen recalled more words than those who received 21% oxygen, which shows 30% oxygen supply has influenced positively on memory cognitive performance. When 30% concentration oxygen is supplied, the blood oxygen saturation in the task phases was increased and the heart rate decreased when comparing to 21%. It means that 30% oxygen can stimulate brain activation by increasing actual blood oxygen concentration in the process of cognitive performance, and the heart rate decreases because enough oxygen is supplied to process the cognitive performance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.109-110
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• 2007

Plasma etching process에서 magnetic field 영향에 관한 연구이다. High level dry etch process를 위해서는 high density plasma(HDP)가 요구된다. HDP를 위해서 MERIE(Magnetical enhancement reactive ion etcher) type의 설비가 사용되며 process chamber side에 4개의 magnetic coil을 사용한다. 이런 magnetic factor가 특히 wafer edge부문에 plasma charging에 의한 damage를 유발시키고 이로 인해 device Vth(Threshold voltage)가 shift 되면서 제품의 program 동작 문제의 원인이 되는 것을 발견하였다. 이번 연구에서 magnetic field와 관련된 plasma charge damage를 확인하고 damage free한 공정조건을 확보하게 되었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.307.2-307.2
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• 2016

In this study, we synthesized Au nanoparticles (AuNPs) in polyacrylonitrile (PAN) thin films using a simple annealing process in the solid phase. The synthetic conditions were systematically controlled and optimized by varying the concentration of the Au salt solution and the annealing temperature. X-ray photoelectron spectroscopy (XPS) confirmed their chemical state, and transmission electron microscopy (TEM) verified the successful synthesis, size, and density of AuNPs. Au nanoparticles were generated from the thermal decomposition of the Au salt and stabilized during the cyclization of the PAN matrix. For actual device applications, previous synthetic techniques have required the synthesis of AuNPs in a liquid phase and an additional process to form the thin film layer, such as spin-coating, dip-coating, Langmuir-Blodgett, or high vacuum deposition. In contrast, our one-step synthesis could produce gold nanoparticles from the Au salt contained in a solid matrix with an easy heat treatment. The PAN:AuNPs composite was used as the charge trap layer of an organic nano-floating gate memory (ONFGM). The memory devices exhibited a high on/off ratio (over $10^6$), large hysteresis windows (76.7 V), and a stable endurance performance (>3000 cycles), indicating that our stabilized PAN:AuNPs composite film is a potential charge trap medium for next generation organic nano-floating gate memory transistors.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.66-79
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• 2008

Several oxides have recently been reported to have resistance-switching characteristics for nonvolatile memory (NVM) applications. Both binary and ternary oxides demonstrated great potential as resistive-switching memory elements. However, the switching mechanisms have not yet been clearly understood, and the uniformity and reproducibility of devices have not been sufficient for gigabit-NVM applications. The primary requirements for oxides in memory applications are scalability, fast switching speed, good memory retention, a reasonable resistive window, and constant working voltage. In this paper, we discuss several materials that are resistive-switching elements and also focus on their switching mechanisms. We evaluated non-stoichiometric polycrystalline oxides ($Nb_2O_5$, and $ZrO_x$) and subsequently the resistive switching of $Cu_xO$ and heavily Cu-doped $MoO_x$ film for their compatibility with modem transistor-process cycles. Single-crystalline Nb-doped $SrTiO_3$ (NbSTO) was also investigated, and we found a Pt/single-crystal NbSTO Schottky junction had excellent memory characteristics. Epitaxial NbSTO film was grown on an Si substrate using conducting TiN as a buffer layer to introduce single-crystal NbSTO into the CMOS process and preserve its excellent electrical characteristics.