• Journal of Korea Multimedia Society
• /
• v.2 no.1
• /
• pp.80-88
• /
• 1999

In this paper, we propose a Special Memory for Graphics(SMGRA) which accelerates memory access time for graphics operations. The SMGRA has a rectangular array memory architecture which has already proposed by Whelan to process pixels in the rectangle area simultaneously, but the SMGRA should improve address decoding time and reduce the number of address pins by using address multiplexing scheme. The SMGRA has a Z-value comparator in the DRAM which is to convert read-modify-write Z buffer into single-write only operation that improves approximately 50% frame buffer access bandwidth.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1998.11a
• /
• pp.13-16
• /
• 1998

An anomalous current characteristics which show the superposition of a low current level and high current level at the subthreshold region when SONOSFETs are in memory states were investigated. We have assumed this phenomena were resulted from the effect of parasitic transistors by LOCOS isolation and were modeled to a parallel equivalent circuit of one memory transistor and two parasitic transistors. Theoretical curves are well fitted in measured log I$_{D}$-V$_{G}$ curves independent of channel width of memory devices. The difference between low current level and high current level is apparently decreased with decrease of channel width of devices because parasitic devices dominantly contribute to the current conduction with decrease of channel width of memory devices. As a result, we concluded that the LOCOS isolation has to selectively adopt in the design of process for charge-trap type NVSM.VSM.

• Journal of Institute of Control, Robotics and Systems
• /
• v.10 no.11
• /
• pp.976-980
• /
• 2004

This study has introduced how to make conducting shape memory polyurethane(CSMPu) as a possible application to smart actuators. Different from conventional polyurethane, CSMPu can have a high conductivity and then electric power supplies enough energy to deform. To prepare conducting polyurethane, carbon nanotubes were incorporated into shape memory polyurethane. Basic experiments to reveal its characteristics have been conducted for a development of actuators. From the results conducted in the present study, optimized conditions for the process of actuating deformation were found. Thermo-electric characteristics such as the relation between temperature and specific resistance and trend curves of resistance variations according to elongations were measured. These data provided a strong possibility of CSMPu as a smart actuator.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.1
• /
• pp.51-65
• /
• 2008

The article presents the recent research development in polymer ferroelectric non-volatile memory. A brief overview is given of the history of ferroelectric memory and device architectures based on inorganic ferroelectric materials. Particular emphasis is made on device elements such as metal/ferroelectric/metal type capacitor, metal-ferroelectric-insulator-semiconductor (MFIS) and ferroelectric field effect transistor (FeFET) with ferroelectric poly(vinylidene fluoride) (PVDF) and its copolymers with trifluoroethylene (TrFE). In addition, various material and process issues for realization of polymer ferroelectric non-volatile memory are discussed, including the control of crystal polymorphs, film thickness, crystallization and crystal orientation and the unconventional patterning techniques.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.997-998
• /
• 2008

In this paper, we proposed a reduced memory overdrive architecture. Proposed overdrive architecture consists of 2D-DWT filter, BLI and Color Conversion block. For Frame Memory reduction we eliminated HH data in DWT-IDWT process and converted color space RGB into YCbCr. Consequently, we reduced Frame Memory about 50%.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.24 no.5
• /
• pp.55-61
• /
• 2010

When we design the control system used Programmable Logic Controller(PLC) by Sequential Function Chart(SFC), if we use a SFC, it is easy to know the sequential flow of control, to maintenance the controller and to describe a program. We program a SFC by a unique sequence, an alternative sequence and a parallel sequence. If we program a SFC by a alternative sequence, the memory size of a alternative sequence must be larger than the memory size of a unique sequence. Therefore this thesis show an efficient method to reduce a memory size and we confirmed its feasibility through actual example.

• Journal of the Korean Society of Safety
• /
• v.29 no.4
• /
• pp.28-33
• /
• 2014

Recently, the actuator worked by the driving recovery-force of the thermo elastic martensitic transformation of shape memory alloys(SMA) has been studied. This paper presents a study on the fatigue life of shape memory alloy (SMA) actuators undergoing thermally induced martensitic phase transformation under various stress levels. shape memory recoverable stress and strain of Ti-44.5at.%Ni-8at.%Cu alloys were by means of constant temperature tensile tests. Differential scanning calorimetry (DSC) was employed in order to investigate the transformation characteristics of the alloy before the tests. the results were summarized as follows. The martensite inducing stress incerased with the increasing of the Cu-contents. The fatigue life decreased with the increasing of the test load and the Cu-content. The data acquired will be very useful during the design process of an SMA NiTiCu element as a functional part of an actuator.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.17 no.1
• /
• pp.59-65
• /
• 2022

Virtual memory is used as the method to ensure the safety of the system through memory protection in the real-time system. TLB miss caused by using virtual memory makes the real-time system WCET more pessimistically. TLB lockdown can be applied as a method to improve this problem. However, processors with limited TLB lockdown entries, a selection criterion is needed to efficiently utilize the TLB lockdown entry. In this paper, the most frequently accessed virtual pages in the process are applied to the TLB lockdown by analyzing memory profiling. The results showed that micro data TLB miss stall cycle and main data TLB miss stall cycle of the processor decreased by at least 4.7% and up to 29.7%.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.4
• /
• pp.53-58
• /
• 2023

The storage capacity of 3D-NAND flash memory has been enhanced by the multi-layer dielectrics. The deposition process has become more challenging due to the tight process margin and the demand for accurate process control. To reduce product costs and ensure successful processes, process diagnosis techniques incorporating artificial intelligence (AI) have been adopted in semiconductor manufacturing. Recently there is a growing interest in process diagnosis, and numerous studies have been conducted in this field. For higher model accuracy, various process and sensor data are required, such as optical emission spectroscopy (OES), quadrupole mass spectrometer (QMS), and equipment control state. Among them, OES is usually used for plasma diagnostic. However, OES data can be distorted by viewport contamination, leading to misunderstandings in plasma diagnosis. This issue is particularly emphasized in multi-dielectric deposition processes, such as oxide and nitride (ON) stack. Thus, it is crucial to understand the potential misunderstandings related to OES data distortion due to viewport contamination. This paper explores the potential for misunderstanding OES data due to data distortion in the ON stack process. It suggests the possibility of excessively evaluating process drift through comparisons with a QMS. This understanding can be utilized to develop diagnostic models and identify the effects of viewport contamination in ON stack processes.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.59 no.6
• /
• pp.1095-1102
• /
• 2010

This paper presents an equalizer reducing CCI(cell-to-cell interference) in MLC NAND flash memory. High growth of the flash memory market has been driven by two combined technological efforts that are an aggressive scaling technique which doubles the memory density every year and the introduction of MLC(multi level cell) technology. Therefore, the CCI is a critical factor which affects occurring data errors in cells. We introduced an equation of CCI model and designed an equalizer reducing CCI based on the proposed equation. In the model, we have been considered the floating gate capacitance coupling effect, the direct field effect, and programming methods of the MLC NAND flash memory. Also we design and verify the proposed equalizer using Matlab. As the simulation result, the error correction ratio of the equalizer shows about 20% under 20nm NAND process where the memory channel model has serious CCI.