• Biomolecules & Therapeutics
• /
• v.26 no.4
• /
• pp.368-373
• /
• 2018

Rapid eye movement (REM) sleep has an essential role in the process of learning and memory in the hippocampus. It has been reported that linalool, a major component of Lavandula angustifolia, has antioxidant, anti-inflammatory, and neuroprotective effects, along with other effects. However, the effect of linalool on the cognitive impairment and behavioral alterations that are induced by REM-sleep deprivation has not yet been elucidated. Several studies have reported that REM-sleep deprivation-induced memory deficits provide a well-known model of behavioral alterations. In the present study, we examined whether linalool elicited an anti-stress effect, reversing the behavioral alterations observed following REM-sleep deprivation in mice. Furthermore, we investigated the underlying mechanism of the effect of linalool. Spatial memory and learning memory were assessed through Y maze and passive avoidance tests, respectively, and the forced swimming test was used to evaluate anti-stress activity. The mechanisms through which linalool improves memory loss and behavioral alterations in sleep-deprived mice appeared to be through an increase in the serotonin levels. Linalool significantly ameliorated the spatial and learning memory deficits, and stress activity observed in sleep-deprived animals. Moreover, linalool led to serotonin release, and cortisol level reduction. Our findings suggest that linalool has beneficial effects on the memory loss and behavioral alterations induced by REM-sleep deprivation through the regulation of serotonin levels.

• Proceedings of the Korean Information Science Society Conference
• /
• 2003.10a
• /
• pp.196-198
• /
• 2003

Virtually every digital signal processors(DSPs) support on-chip multi- memory banks that allow the processor to access multiple words of data from memory in a single instruction cycle. Also, all existing fixed-point DSPs have irregular architecture of heterogeneous register which contains multiple register files that are distributed and dedicated to different sets of instructions. Although there have been several studies conducted to efficiently assign data to multi-memory banks, most of them assumed processors with relatively simple, homogeneous general-purpose resisters. Therefore, several vendor-provided compilers fer DSPs were unable to efficiently assign data to multiple data memory banks. thereby often failing to generate highly optimized code fer their machines. This paper presents an algorithm that helps the compiler to efficiently assign data to multi- memory banks. Our algorithm differs from previous work in that it assigns variables to memory banks in separate, decoupled code generation phases, instead of a single, tightly-coupled phase. The experimental results have revealed that our decoupled algorithm greatly simplifies our code generation process; thus our compiler runs extremely fast, yet generates target code that is comparable In quality to the code generated by a coupled approach

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.34 no.2
• /
• pp.179-192
• /
• 2024

macOS presents challenges for memory data acquisition due to its proprietary system architecture, closed-source kernel, and security features such as System Integrity Protection (SIP), which are exclusive to Apple's product line. Consequently, conventional memory acquisition tools are often ineffective or require system rebooting. This paper analyzes the status and limitations of existing memory forensics research and tools related to macOS. We investigate methods for memory acquisition and analysis across various macOS versions. Our findings include the development of a practical memory acquisition and analysis process for digital forensic investigations utilizing OSXPmem and dd tools for memory acquisition without system rebooting, and Volatility 2, 3 for memory data analysis.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.25 no.2
• /
• pp.100-104
• /
• 2012

Fin-type SONOS (silicon-oxide-nitride-oxide-silicon) flash memory has emerged as novel devices having superior controls over short channel effects(SCE) than the conventional SONOS flash memory devices. However despite these advantages, these also exhibit undesirable characteristics such as corner effect. Usually, the corner effect deteriorates the performance by increasing the leakage current. In this paper, the corner effect of fin-type SONOS flash memory devices is investigate by 3D Process and device simulation and their electrical characteristics are compared to conventional SONOS devices. The corner effect has been observed in fin-type SONOS device. The reason why the memory characteristic in fin-type SONOS flash memory device is not improved, might be due to existing undesirable effect such as corner effect as well as the mutual interference of electric field in the fin-type structure as reported previously.

• 제어로봇시스템학회:학술대회논문집
• /
• 1989.10a
• /
• pp.372-376
• /
• 1989

One of the major difficulties with modular approach model of separation process simulation is initial guess problem. Only accurate initial guess make the problem converge and large computer memory and calculating time are required. In this study, we use the initial bottom guess value same as given feed condition and update the value the .theta.method. So we examine;(1)the problem converges using initial guess with large range, (2)computer memory and calculating time are reduced considerably.

• Proceedings of the KIEE Conference
• /
• 2006.10a
• /
• pp.105-106
• /
• 2006

The ferroelectric materials of the PZT, SBT attracted much attention for application to ferroelectric random access memory (FRAM) devices. Through the last decade, the lead zirconate titanate (PZT) is one of the most attractive perovskite-type materials for the ferroelectric products due to its higher remanant polarization and the ability to withstand higher coercive fields. FRAM has been currently receiving increasing attention for one of future memory devices due to its ideal memory properties such as non-volatility, high charge storage, and faster switching operations. In this study, we first applied the damascene process using chemical mechanical polishing (CMP) to the fabricate the $Pb_{1.1}(Zr_{0.52}Ti_{0.48})O_3$ thin film capacitor in order to solve the problems of plasma etching such as low etching profile and ion charging. The structural characteristics were compared with specimens before and after CMP process of PZT films. The scanning electron microscopy (SEM) analysis was performed to compare the morphology surface characteristics of $Pb_{1.1}(Zr_{0.52}Ti_{0.48})O_3$ capacitors. The densification by the vertical sidewall patterning and charging-free ferroelectric capacitor could be obtained by the damascene process without remarkable difference of the characteristics.

• Design & Manufacturing
• /
• v.10 no.2
• /
• pp.50-54
• /
• 2016

In the semiconductor industry the final products were checked for several environments before sell the products. The burning test of memory and chip was implemented in reliability for all of parts. The memory and chip were developed to high density memory and high performance chip, so circuit design was also high integrated and the test bed was needed to be thin and fine pitch socket. LGA(Land Grid Array) IC socket with thin wall thickness was designed to satisfy this requirement. The LGA IC socket plastic part was manufacture by injection molding process, it was needed accuracy, stiffness and suit resin with high flowability. In this study, injection molding process analysis was executed for 2 and 4 cavities moldings with runner, gate and sprue. The warpage analysis was also implemented for further gate removal process. Through the analyses the total deformations of the moldings were predicted within maximum 0.05mm deformation. Finally in consideration of these results, 2 and 4 cavities molds were designed and made and tested in injection molding process.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.1
• /
• pp.105-111
• /
• 2013

We have developed an analog associative memory implemented with an analog array which has linear writing and erasing characteristics. The associative memory adopts a winner-take-all strategy. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We also present a system architecture that enables highly-paralleled fast writing and quick readout as well as high integration density. A multiple memory cell configuration is also presented for achieving higher integration density, quick readout, and fast writing. The system technology presented here is ideal for a real time recognition system. We simulate the function of the mechanism by menas of Hspice with $1.2{\mu}$ double poly CMOS parameters of MOSIS fabrication process.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.3
• /
• pp.28-39
• /
• 1994

We experimented on memory multichip modules to increase the packing density of memory devices and to improve their electrical characteristics. A 128K$\times$8bit SRAM module was made of four 32K$\times$8bit SRAM memory chips. The memory multichip module was constructed on a low-cost double sided PCB(printed circuit boared) substrate. In the process of fabricating a multichip module. we focused on the improvement of its electrical characteristics. volume, and weight by employing bare memory chips. The characteristics of the bare chip module was compared with that of the module with four packaged chips. We conducted circuit routing with a PCAD program, and found the followings: the routed area for the module with bare memory chips reduced to a quarter of that area for module with packaged memory chips. 1/8 in volume, 1/5 in weight. Signal transmission delay times calculated by using transmission line model was reduced from 0.8 nsec to 0.4 nsec only on the module board, but the coupling coefficinet was not changed. Thus, we realized that the electrical characteristics of multichip packages on PCB board be improved greatly when using bare memory chips.

• Journal of the Semiconductor & Display Technology
• /
• v.19 no.3
• /
• pp.118-123
• /
• 2020

In this paper, the design method of asynchronous nonvolatile memory module that can efficiently process and store large amounts of data without loss when the power turned off is proposed and implemented. PSRAM, which takes advantage of DRAM and SRAM, was used for data processing, and NAND flash memory was used for data storage and backup. The problem of a lot of signal interference due to the characteristics of memory devices was solved through PCB design using high-density integration technology. In addition, a boost circuit using the super capacitor of 0.47F was designed to supply sufficient power to the system during the time to back up data when the power is off. As a result, an asynchronous nonvolatile memory module was designed and implemented that guarantees reliability and stability and can semi-permanently store data for about 10 years. The proposed method solved the problem of frequent data loss in industrial sites and presented the possibility of commercialization by providing convenience to users and managers.