• Title/Summary/Keyword: Preamble searcher

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Design of high-speed preamble searcher adequate for RACH preamble structure in WCDMA reverse link receiver (RACH 프리앰블 구조에 적합한 WCDMA 역방향 링크 수신기용 고속 프리앰블 탐색기의 설계)

  • 정은선;도주현;이영용;정성현;최형진
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.8A
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    • pp.898-908
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    • 2004
  • In this paper, we propose a high speed preamble searcher feasible for RACH(Random Access Channel) preamble structure in WCDMA reverse link receiver. Unlike IS-95, WCDMA system uses AISMA(Acquisition Indication Sense Multiple Access) process. Because of the time limit between RACH preamble transmission and AI(Acquisition Indicators), and the restriction on the number of RACH signatures assigned to RACH preamble, fast acquisition indication is required for efficient operation. The preamble searcher proposed in this paper is based on 2-antenna system and has adopted FHT algorithm that has the radix-2 16 point FFT structure. The acquisition speed using FHT is 64 times faster than the conventional method that correlates each signature. Based on their fast aquisition scheme, we improved the acquisition performance by calculating the correlation up to the 4096 chips of the total preamble length. The performance is analyzed by using Neyman-pearson method. The proposed algorithm has been applied for the implementation of WCDMA reverse link receiver modem successfully.

Initial Timing Acquisition for Binary Phase-Shift Keying Direct Sequence Ultra-wideband Transmission

  • Kang, Kyu-Min;Choi, Sang-Sung
    • ETRI Journal
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    • v.30 no.4
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    • pp.495-505
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    • 2008
  • This paper presents a parallel processing searcher structure for the initial synchronization of a direct sequence ultra-wideband (DS-UWB) system, which is suitable for the digital implementation of baseband functionalities with a 1.32 Gsample/s chip rate analog-to-digital converter. An initial timing acquisition algorithm and a data demodulation method are also studied. The proposed searcher effectively acquires initial symbol and frame timing during the preamble transmission period. A hardware efficient receiver structure using 24 parallel digital correlators for binary phase-shift keying DS-UWB transmission is presented. The proposed correlator structure operating at 55 MHz is shared for correlation operations in a searcher, a channel estimator, and the demodulator of a RAKE receiver. We also present a pseudo-random noise sequence generated with a primitive polynomial, $1+x^2+x^5$, for packet detection, automatic gain control, and initial timing acquisition. Simulation results show that the performance of the proposed parallel processing searcher employing the presented pseudo-random noise sequence outperforms that employing a preamble sequence in the IEEE 802.15.3a DS-UWB proposal.

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Fast code synchronization method of the DS-SS/TDMA control channel for satellite communication (직접대역확산 방식의 시분할 다중접속 위성통신 제어채널 고속 부호동기 방법)

  • Ryu, Young-Jae
    • Journal of Satellite, Information and Communications
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    • v.4 no.1
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    • pp.14-20
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    • 2009
  • This paper describes synchronization concept and algorithm of the reverse DS-SS/TDMA control channel to handle satellite terminals which are distributed through the mission area. Military satellite control channel should have ECCM capabilities and handle more than several hundreds satcom terminals simultaneously. DS-SS/TDMA control channel can satisfy these demand but it spend much synchronization time. Proposed algorithm insert the preamble which is divided with several short sub bins prior to control data and use the parallel matched filtering searcher for each sub bin. As a result of the test, proposed algorithm can acquire most of control channel packet successfully within several milliseconds in severe jamming environment.

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