• Journal of Power Electronics
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• v.19 no.5
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• pp.1122-1132
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• 2019

In this paper, aiming at high-voltage applications, transformer windings schemes of multiple-output two-transistor flyback converters are investigated, which are mainly based on the stray capacitances effect. First, based on a transformer model including equivalent stray capacitors, the operational principle of the converter is presented, and the main influence of its stay capacitors is determined. Second, the windings structures of the transformer are analyzed and designed based on the stray capacitances effect. Third, the windings arrangements of the transformer are analyzed and designed through a coupling analysis of the secondary windings and a stray capacitance analysis between the primary and secondary windings. Finally, the analysis and design conclusions are verified by experimental results obtained from a 60W laboratory prototype of a multiple-output two-transistor flyback converter.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.1
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• pp.14-19
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• 2001

When the high power transistor is used for amplifier in microwave frequency, the bias of transistor is usually AB-class or B-c1ass because of power efficiency. The sweet spot point having small IMD signal compared with near neighborhood exicts frequently in the high power transistor using AB class bias or B-class bias. On the sweet spot, the magnitude and phase of the main and IMD signal of HPA output change as the input signal power change, respective the relative phase on the sweet spot changes rapidly. If we know exactly the magnitude and phase characteristics of IMD signal, we can design a more adequate linearizer and understand the characteristics of transistor. In this paper the magnitude and phase of the main and IMD signal of HPA output on the sweet spot are measured using the designed hardware.

• ETRI Journal
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• v.27 no.5
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• pp.579-584
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• 2005

A CMOS direct-conversion mixer with a single transistor-level topology is proposed in this paper. Since the single transistor-level topology needs smaller supply voltage than the conventional Gilbert-cell topology, the proposed mixer structure is suitable for a low power and highly integrated RF system-on-a-chip (SoC). The proposed direct-conversion mixer is designed for the multi-band ultra-wideband (UWB) system covering from 3 to 7 GHz. The conversion gain and input P1dB of the mixer are about 3 dB and -10 dBm, respectively, with multi-band RF signals. The mixer consumes 4.3 mA under a 1.8 V supply voltage.

• Journal of the Korean Institute of Telematics and Electronics
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• v.16 no.2
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• pp.7-14
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• 1979

Design considerations of I2L are discussed with particular emphasis on the upward current gain of the npn transistor, 6J Several test structures have been fabricated to measure the DC and AC characteristics of the I2L basic cell and the base current components of the npn transistor. A T flip-flop has also been designed and fabricated using the I2L technology. The upward current gain of 10 the speed -power product of the 2.6pJ/gate and the minimum propagation delay time of 36 nsec have been obtained from the test structure. The maxmum toggle frequency of the T flip -flop has been measured to be 3.5 MHz.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.10
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• pp.25-34
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• 1995

A new vertical power MOSFET with over-current protection capability is proposed. The MOSFET consists of main power MOSFET cell, sensing MOSFET cell and lateral npn bipolar transistor. The proposed MOSFET may be fabricated by a conventional DMOS process without any additional fabrication step. Overcurrent state is sensed by the newly designed lateral bipolar transistor. Mixed-mode simulations proved that the overcurrent protection is achieved by the proposed MOSFET successfully with a small protection area less than 0.2 % of the total die area.

• Korean Journal of Materials Research
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• v.27 no.11
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• pp.590-596
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• 2017

We demonstrated a CNT synaptic transistor by integrating 6,6-phenyl-C61 butyric acid methyl ester(PCBM) molecules as charge storage molecules in a polyimide(PI) dielectric layer with carbon nanotubes(CNTs) for the transistor channel. Specifically, we fabricated and compared three different kinds of CNT-based synaptic transistors: a control device with $Al_2O_3/PI$, a single PCBM device with $Al_2O_3/PI:PCBM$(0.1 wt%), and a double PCBM device with $Al_2O_3/PI:PCBM$(0.1 wt%)/PI:PCBM(0.05 wt%). Statistically, essential device parameters such as Off and On currents, On/Off ratio, device yield, and long-term retention stability for the three kinds of transistor devices were extracted and compared. Notably, the double PCBM device exhibited the most excellent memory transistor behavior. Pulse response properties with postsynaptic dynamic current were also evaluated. Among all of the testing devices, double PCBM device consumed such low power for stand-by and its peak current ratio was so large that the postsynaptic current was also reliably and repeatedly generated. Postsynaptic hole currents through the CNT channel can be generated by electrons trapped in the PCBM molecules and last for a relatively short time(~ hundreds of msec). Under one certain testing configuration, the electrons trapped in the PCBM can also be preserved in a nonvolatile manner for a long-term period. Its integrated platform with extremely low stand-by power should pave a promising road toward next-generation neuromorphic systems, which would emulate the brain power of 20 W.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.1-6
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• 2016

In this paper, we introduce the characteristics of a vertical PNP transistor that improves start current by decreasing quiescent current with suppressing the parasitic transistor. In order to suppress the parasitic effect, we designed a vertical PNP transistor which suppresses parasitic PNP transistor by using the "DN+ links" without changing the circuit and made a LDO regulator using a standard IC processor. HFE of the fabricated parasitic PNP transistor decreased from conventional 18 to 0.9. Starting current of the LDO regulator made of the vertical PNP transistor using the improved "DN+ linked" structure is reduced from the conventional starting current of 90mA to 32mA. As the result, we developed a LDO regulator which consumes lower power in the standby state.

• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.243-248
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• 2008

This paper proposes a low-power carry look-ahead adder using multi-threshold voltage CMOS. The designed adder is compared with conventional CMOS adder. The propagation delay time is reduced by using low-threshold voltage transistor in the critical path. Also, the power consumption is reduced by using high-threshold voltage transistor in the shortest path. The other logic block is implemented with normal-threshold transistor. Comparing with the conventional CMOS circuit, the proposed circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.497-505
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• 2016

The two-dimensional (2D) Discrete Cosine Transform (DCT) is used widely in image and video processing systems. The perception of human visualization permits us to design approximate rather than exact DCT. In this paper, we propose a digital implementation of 16-point approximate 2D DCT architecture based on one-dimensional (1D) DCT and Modified Gate Diffusion Input (MGDI) technique. The 8-point 1D Approximate DCT architecture requires only 12 additions for realization in digital VLSI. Additions can be performed using the proposed 8 transistor (8T) MGDI Full Adder which reduces 2 transistors than the existing 10 transistor (10T) MGDI Full Adder. The Approximate MGDI 2D DCT using 8T MGDI Full adders is simulated in Tanner SPICE for $0.18{\mu}m$ CMOS process technology at 100MHZ.The simulation result shows that 13.9% of area and 15.08 % of power is reduced in the 8-point approximate 2D DCT, 10.63 % of area and 15.48% of power is reduced in case of 16-point approximate 2D DCT using 8 Transistor MGDI Full Adder than 10 Transistor MGDI Full Adder. The proposed architecture enhances results in terms of hardware complexity, regularity and modularity with a little compromise in accuracy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.15-21
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• 2004

In this paper a new structure of BJT is proposed to improve the saturation voltage characteristics so that it can be used to the low power switching devices. In the case of the conventional finger transistor(FT), the saturation voltage is so high that it dose not satisfy the requirements for the low power device. So the other multi base island transistor(MBIT) is suggested and its saturation voltage is so low in the region of low current that it satisfy the requirement for the low power switching devices, but in region of the high current the saturation voltage tends to increase so that it does not satisfy the requirements for the low power switching devices. So in this paper a new structure of folded back electrode transistor(FBET) is proposed and the characteristics is investigated. When the new structure is applied the emitter area is increased by 35 % so the saturation voltage is reduced by 30 % at the low current region and the contact area is increased by 92 % so the saturation voltage is reduced by totally f % at the high current region with the reduction of 30 % by the increase of the emitter area and the reduction of 7 % by the increase of the emitter contact area.