• Journal of IKEEE
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• v.15 no.4
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• pp.319-323
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• 2011

In this paper presents a new model of dual-mode synchronous buck converter with dynamic control for mobile applications was proposed. The proposed circuit can operate at 2.5MHz with supply voltage 2.5V to 5V for low ripple and minimum inductor and capacitor size, which is suitable for single-cell lithium-ion battery supply mobile applications. For high efficiency, the proposed circuit adopts synchronous type and dynamic control. The proposed circuit is designed by using the device parameter of TSMC 0.18um BCD process and the performance is evaluated by Cadence spectre. Experimental board level results show the maximum conversion efficiency is 96% at 100mA load current.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.41-43
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• 1999

Among the feffoelectric thin films that have been widely investigated for ferroelectric random access memory (FRAM) applications, SrBi$_2$Ta$_2$$O_{9}$ thin film is appropriate to memory capacitor materials for its excellent fatigue endurance. However, very few studies on etch properties of SBT thin film have been reported although dry etching is an area that demands a great deal of attention in the very large scale integrations. In this study, the a SrBi$_2$Ta$_2$$O_{9}$ thin films were etched by using magnetically enhanced inductively coupled Ar/CHF$_3$ plasma. Etch properties, such as etch rate, selectivity, and etched profile, were measured according to gas mixing ratio of CHF$_3$(Ar$_{7}$+CHF$_3$) and the other process conditions were fixed at RF power of 600 W, dc bias voltage of 150 V, chamber pressure of 10 mTorr. Maximum etch rate of SBT thin films was 1750 A77in, under CHF$_3$(Ar+CHF$_3$) of 0.1. The selectivities of SBT to Pt and PR were 1.35 and 0.94 respectively. The chemical reaction of etched surface were investigated by X-ray photoelectron spectroscopy (XPS) analysis. The Sr and Ta atoms of SBT film react with fluorine and then Sr-F and Ta-F were removed by the physical sputtering of Ar ion. The surface of etched SBT film with CHF$_3$(Ar+CHF$_3$) of 0.1 was analyzed by secondary ion mass spectrometer (SIMS). Scanning electron microscopy (SEM) was used for examination of etched profile of SBT film under CHF$_3$(Ar+CHF$_3$) of 0.1 was about 85˚.85˚.˚.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.1
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• pp.25-33
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• 1998

In this paper, we describe a single-gate MESFET mixer at PCS(Personal Communication Service) frequency band. The PCS frequency band is 1965~2025 MHz in FR and 140 MHz in IF irrespectly. The design of the mixer was executed by microwave simulator, EEsof Libra. The matching network is consisted of rectangular inductor, MIM capacitor and open stub. The ma- nufacture work was accomplished by the micro-pen and wedge-bonder. The mixer showed $6.69\pm0.65$ dB of conversion gain, $-14.9\pm3.5$dB of RF reflection coefficient and 57.83 dB of LO/IF isolation at 10 dBm of LO power when LO frequency is 1855 MHz. When this mixer is used at PCS terminal, IF-amplifier which compensates the conversion loss of diode mixer may be omitted.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.12 no.1
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• pp.35-44
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• 1998

In this paper, input LC filter design of diode rectifiers considering filter V A rating reduction has been propoesd. It consisted of an input LC parallel resonent tank whose inductor and capacitor values are se$.$ lected so that the input filter presents an infinite impedance to harmonic input ac current component. The operation of proposed input filter has been analyzed in detail under steady state conditions. Performance evaluation and related design data have been provided on Per Unit basis for the proper implementation of diode rectification system. Finally, Detailed input and output current analysis has shown that the proposed input filter yield high quality input ac current waveforms, in particular, high input power factor values and more reliabilty which reducing the V A rating of passive components as compared to the standard type LC filter.filter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1A
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• pp.134-141
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• 2007

This paper presents a frequency synthesizer(FS) for 5.2GHz/2.4GHz dual band wireless applications which is designed in a standard $0.18{\mu}m$ CMOS1P6M process. The 2.4GHz frequency is obtained from the 5.2GHz output frequency of Voltage Controlled Oscillator (VCO) by using the Switched Capacitor (SC) and the divider-by-2. Power dissipations of the proposed FS and VCO are 25mW and 3.6mW, respectively. The tuning range of VCO is 700MHz and the locking time is $4{\mu}s$. The simulated phase noise of PLL is -101.36dBc/Hz at 200kHz offset frequency from 5.0GHz with SCA circuit on.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.7
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• pp.1151-1160
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• 2016

In recent years, the energy storage systems such as LiB, NaS, RFB(Redox-Flow Battery), Super- capacitor, pumped hydro storage, flywheel, CAES(Compressed Air Energy Storage) and so on have received great attention as practical solutions for the power supply problems. They can be used for various purpose of peak shaving, load leveling and frequency regulation, according to the characteristics of each ESS(energy storage system). This paper will focus at 1 MWh RFB system, which is being developed through the original technology project of energy material. The output of ESS is mainly characterized by C-rate, which means that the total rated capacity of battery will be delivered in 1 hour. And it is a very important factor in the ESS operation scheduling. There can be several options according to the operation intervals 15, 30 and 60minutes. The operation scheduling is based on the optimization to minimize the daily electricity cost. This paper analyzes the cost-saving effects by the each operating time-interval in case that the RFB ESS is optimally scheduled for peak shaving and load leveling.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.1
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• pp.37-42
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• 2021

This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.

• Journal of Powder Materials
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• v.28 no.6
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• pp.470-477
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• 2021

Energy storage systems should address issues such as power fluctuations and rapid charge-discharge; to meet this requirement, CoFe₂O₄ (CFO) spinel nanoparticles with a suitable electrical conductivity and various redox states are synthesized and used as electrode materials for supercapacitors. In particular, CFO electrodes combined with carbon nanofibers (CNFs) can provide long-term cycling stability by fabricating binder-free three-dimensional electrodes. In this study, CFO-decorated CNFs are prepared by electrospinning and a low-cost hydrothermal method. The effects of heat treatment, such as the activation of CNFs (ACNFs) and calcination of CFO-decorated CNFs (C-CFO/ACNFs), are investigated. The C-CFO/ACNF electrode exhibits a high specific capacitance of 142.9 F/g at a scan rate of 5 mV/s and superior rate capability of 77.6% capacitance retention at a high scan rate of 500 mV/s. This electrode also achieves the lowest charge transfer resistance of 0.0063 Ω and excellent cycling stability (93.5% retention after 5,000 cycles) because of the improved ion conductivity by pathway formation and structural stability. The results of our work are expected to open a new route for manufacturing hybrid capacitor electrodes containing the C-CFO/ACNF electrode that can be easily prepared with a low-cost and simple process with enhanced electrochemical performance.

• Journal of Platform Technology
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• v.11 no.3
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• pp.68-75
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• 2023

This paper discusses methods for increasing the germination rate of barley seeds using low direct and alternating current power below 110V. The experimental apparatus used here is a parallel plate, with the bottom surface of the plate designed to be wider than the top surface to increase the size of the electrostatic field. As a result, three different magnitudes of electrostatic fields were created on the plates: the first ranging from 400V/cm to 600V/cm, the second from 600V/cm to 900V/cm, and the third from 2200V/cm to 2400V/cm. The finite difference method was applied to analyze the electrostatic field inside the parallel plate. The plant seeds used in the experiments were barley seeds produced domestically. The average germination rate of barley seeds using the presented electrostatic field in this paper was 57%, while it was 65% when using a microwave of 2.45GHz, compared to a control group with a result of 31%. An important difference between using the electrostatic field and the 2.45GHz microwave is the dry method and wet method. When applying these two methods to practical seed germination, it is necessary to consider the advantages and disadvantages of each experimental approach and choose the appropriate method accordingly.