• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.3
• /
• pp.59-66
• /
• 2015

In this paper, we propose a method of improving the light-load efficiency of DC-DC buck converter using 4bit SAR-ADC (Successive Approximation ADC) for a LDO or a power transistor size selection technique. The proposed circuit selects power transistor sizes depending on load current so that improves the light-load efficiency of the DC-DC buck converter. For this, we select the power transistor size with a cross point of the switching loss and the conduction loss. Also, when the IC operates in standby mode or sleep mode, a LDO mode is selected for improving the efficiency. The proposed circuit selects power transistor sizes(X1, X2, X4, X8) with 4 bits and its efficiency is higher about the maximum of 25% at the light-load than that of a single transistor size. Input voltage and output voltage are 5V and 3.3V for maximum load currents of 500mA.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.7
• /
• pp.37-45
• /
• 1998

A 32-b self-timed parallel carry look-ahead adder (PCLA) designed for 0.5.mum. single threshold low power CMOS technology is demonstrated to operate with 2.7nsec delay at 8mW under 1V power supply. Compared to static PCLA and DPL adder, the self-timed PCLA designed with NORA logic provides the best performance at the power consumption comparable to other adder structures. The wave pipelined clock control play a crucial role in achieving the low power, high performance of this adder by eliminating the unnecessary power consumption due to the short-circuit current during the precharge phase. Th enoise margin has been improved by adopting the physical design of staic CMOS logic structure with controlled transistor sizes.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.28 no.6
• /
• pp.435-443
• /
• 2017

In this study, we analyzed the effects of the common-gate transistor bias of a switching mode CMOS power amplifier. Although the most earier works occured on the transistor sizes of the cascode structure, we showed that the gate bias of the common-gate transistor also influences the overall efficiency of the power amplifier. To investigate the effect of the gate bias, we analyzed the DC power consumption according to the gate bias and hence the efficiency of the power amplifier. From the analyzed results, the optimized gate bias for the maximum efficiency is lower than the supply voltage of the power amplifier. We also found that an excessively low gate bias may degrade the output power and efficiency owing to the effects of the on-resistance of the cascode structure. To verify the analyzed results, we designed a 1.9 GHz switching mode power amplifier using $0.18{\mu}m$ RF CMOS technology. As predicted in the analysis, the maximum efficiency is obtained at 2.5 V, while the supply voltage of power amplifier is 3.3 V. The measured maximum efficiency is 31.5 % with an output power of 29.1 dBm. From the measureed results, we successfully verified the analysis.

• Journal of Electrical Engineering and Technology
• /
• v.12 no.5
• /
• pp.1805-1811
• /
• 2017

Recently, DC systems are considered as efficient electric power systems for renewable energy based clean power generators. This discloses several critical issues that are required to be considered before the installation of the DC systems. First of all, voltage/current switching stress, which is aggravated by large fault current, might damage DC circuit breakers. This problem can be simply solved by applying a superconducting fault current limiter (SFCL) as proposed in this study. It allows a simple use of insulated-gate bipolar transistors (IGBTs) as a DC circuit breaker. To evaluate the proposed resistive type SFCL application to the DC circuit breaker, a DC distribution system is composed of the practical line impedances from the real distribution system in Do-gok area, Korea. Also, to reflect the distributed generation (DG) effects, several DC-to-DC converters are applied. The locations and sizes of the DGs are optimally selected according to the results of previous studies on DG optimization. The performance of the resistive type SFCL applied DC circuit breaker is verified by a time-domain simulation based case study using the power systems computer aided design/electromagnetic transients including DC (PSCAD/ EMTDC(R)).

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.1
• /
• pp.64-71
• /
• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.