• Proceedings of the Korean Society of Medical Physics Conference
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• 2002.09a
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• pp.468-470
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• 2002

We have designed X-ray detection system and multi-channel data acquisition system for Spiral CT application. X-ray detection system consists of scintillator and photodiode. Scintillator converts X-ray into visible light. Photodiode converts visible light into electrical signal. The multi-channel data acquisition system consists of analog, digital, master and backplane board. Analog board detects electrical signal and amplifies signal by 140dB. Digital board consists of MUX(Multiplex) which routes multi-channel analog signal to preamplifier, and ADC(Analog to Digital Converter) which converts analog signal into digital signal. Master board supplies the synchronized clock and transmits the digital data to image reconstructor. Backplane provides electrical power, analog output and clock signal. The system converts the projected X-ray signal over the detector array with large gain, samples the data in each channel sequentially, and the sampled data are transmitted to host computer in a given time frame. To meet the timing limitation, this system is very flexible since it is implemented by FPGA(Field Programmable Gate Array). This system must have a high-speed operation with low noise and high SNR(signal to noise ratio), wide dynamic range to get a high resolution image.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.128-133
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• 2006

This paper describes a high speed interface circuit using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that converts redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, the proposed 1:4 DEMUX (demultiplexer, serial-parallel converter), was designed using a 0.35um standard CMOS technology. Proposed DEMUX is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW. The operating speed of this circuit is limited by the maximum frequency which the 0.35um process has. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 10Gb/s in submicron process of high operating frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.162-170
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• 2015

In the bandpass sampling (BPS), the sampling frequency is lower than the frequency of the signal to be sampled. In this method, the baseband spectrum can be directly obtained by the sampling operation. This makes the frequency down converter unnecessary as well as the receiver's circuit simpler. In the second-order BPS system, two sampling devices are used. When aliasing occurs due to the sampling operation, the aliased component can be cancelled by combining the two sampled signals. In this paper, it is presented a design method of the second-order BPS system when multiple interferences are simultaneously aliased to the signal component. The optimum phase of the interpolant filter is searched for maximizing the signal-to-interference ratio, and a practical formula for the suboptimal phase is derived in terms of the power spectrum profile of the BPS input. A computer simulation has been performed for the proposed second-order BPS system, and it has been shown that the signal-to-interference ratio can be increased by considering multiple aliasing.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.148-158
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• 2012

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S & H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a $0.18{\mu}m$ CMOS technology. The designed circuit show that the modulator achieves 87.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth and differential nonlinearity (DNL) of ${\pm}0.25$ LSB, integral nonlinearity (INL) of ${\pm}0.2$ LSB. Power consumption of delta-sigma modulator is $941.6{\mu}W$. It was decided that N cycles are 200 clock for 16-bits output.

• Korean Journal of Materials Research
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• v.27 no.5
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• pp.281-288
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• 2017

In this study, Fe-Ni slag, converter slag and dephosphorization slag generated from the steel industry, and fly ash or bottom ash from a power plant, were mixed at an appropriate mixing ratio and melted in a melting furnace in a mass-production process for glass ceramics. Then, glass-ceramic products, having a basalt composition with $SiO_2$, $Al_2O_3$, CaO, MgO, and $Fe_2O_3$ components, were fabricated through casting and heat treatment process. Comparison was made of the samples before and after the modification of the process conditions. Glass-ceramic samples before and after the process modification were similar in chemical composition, but $Al_2O_3$ and $Na_2O$ contents were slightly higher in the samples before the modification. Before and after the process modification, it was confirmed that the sample had a melting temperature below $1250^{\circ}C$, and that pyroxene and diopside are the primary phases of the product. The crystallization temperature in the sample after modification was found to be higher than that in the sample before modification. The activation energy for crystallization was evaluated and found to be 467 kJ/mol for the sample before the process modification, and 337 kJ/mol for the sample after the process modification. The degree of crystallinity was evaluated and found to be 82 % before the process change and 87 % after the process change. Mechanical properties such as compressive strength and bending strength were evaluated and found to be excellent for the sample after process modification. In conclusion, the samples after the process modification were evaluated and found to have superior characteristics compared to those before the modification.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1464-1474
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• 1994

GPS(Global Positioning System)is a satellite-based navigation system that we can survey where we are, anywhere and anytime. In this paper, delay-lock loop of the receiver which detects the navigation data is theoretically analyzed, and designed using the digital logic circuit. Also logic operations for the synchronization are analyzed. The designed system consists of the correlator which correlates the received C/A code and the generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock syntheizer which generates the clock of the C/A code generator to control the C/A code phase and clock rate. From the analyses results of the proposed digital delay-lock loop system, the system has the detection propertied over 90% when its input signal power is above-113.98dB. The influence of input signal variation of digital delay loop, which is the input of A/D converter, is investigated and the performance is analyzed with the variation of threshold level via the computer simulation. The logic simulation results show that the designed system detects precisely the GPS navigation data.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.197-199
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• 2002

The invention of VHDL(Very High Speed Integrated Circuit Hardware Description Language), Technical language of Hardware, is a kind of turning point in digital circuit designing, which is being more and more complicated and integrated. Because of its excellency in expression ability of hardware, VHDL is not only used in designing Hardware but also in simulation for verification, and in exchange and conservation, composition of the data of designs, and in many other ways. Especially, It is very important that VHDL is a Technical language of Hardware standardized by IEEE, intenational body with an authority. The biggest problem in modern circuit designing can be pointed out in two way. One is a problem how to process the rapidly being complicated circuit complexity. The other is minimizing the period of designing and manufacturing to survive in a cutthroat competition. To promote the use of VHDL, more than a simple use of simulation by VHDL, it is requested to use VHDL in composing logical circuit with chip manufacturing. And, by developing the quality of designing technique, it can contribute for development in domestic industry related to ASIC designing. In this paper in designing SMPS(Switching mode power supply), programming PWM by VHDL, it can print static voltage by the variable load, connect computer to chip with byteblaster, and download in Max(EPM7064SLCS4 - 5)chip of ALTER. To achieve this, it is supposed to use VHDL in modeling, simulating, compositing logic and product of the FPGA chip. Despite its limit in size and operating speed caused by the specific property of FPGA chip, it can be said that this method should be introduced more aggressively because of its prompt realization after designing.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.35 no.3
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• pp.589-597
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• 2015

Wave energy harvesting system using OWC(Oscillating Water Column) and MB (Movable Body) attached at the caisson breakwater was studied. This system was suggested to maximize wave energy extraction using resonant phenomena of oscillating water column and buoy in wave channel (Park et al., 2014). Not only incident waves but also reflected waves from the breakwater can be used as sources of exciting force for harvesting wave energy efficiently. Using Galerkin finite model based on the linear wave theory (Park, 1991), the performance of the system was evaluated for various damping ratios of power take off system. Numerical results show that the proposed system is excellent in efficiency compared with that of conventional system and the performance of the system is governed by the resonance of oscillating water column in the wave channel. In addition, the additional efforts to minimize viscous damping was found to be necessary because viscous damping occurring in the channel and around the moving buoy is significant in generation efficiency.

• The Journal of the Korea Contents Association
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• v.6 no.1
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• pp.8-13
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• 2006

In this thesis, an automatic door lock system using a dual tone multiple frequency(DTMF) signal generated as pushing the key button of mobile phone is proposed and implemented. This system consists of a transmitter module and a receiver module for processing the DTMF signal of mobile phone. The DTMF signal of mobile phone connected with ear-phone jack enter into the input terminal of DTMF receiver and those are encoded by a code-converter with 4-bits binary format in the DTMF receiver. The encoded output signals are transmitted to the amplitude shift keying(ASK) modulator of transmitter module and the modulated ASK signals which are converted into radio frequency(RF) signals propagate in a free space. The RF signals passed through a free space are demodulated by the ASK demodulator of receiver module and the demodulated ASK signals are sent to a micro-controller unit(MCU). The output signals processed by the MCU are compared with the secreted identification number which is prerecorded in a microprocessor and are transferred to a power relay. If the result is the same, the automatic door lock system opens a door. In the opposite case, it maintains closing the door. The implemented automatic door lock system operates well in mobile environments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.