• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1633-1635
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• 1997

For AMLCD pixel switching device, poly-Si TFT has the advantage of high field effect mobility over a-Si TFT. However, it also has some disadvantage such as large leakage current and more masking steps. We propose a new Inverse Staggered poly-Si TFT with a-Si offset. We have fabricated the new device and verified high ON/OFF current ratio. The device has lower leakage current level than the conventional Inverse Staggered poly-Si TFT and the same number of masking steps compared with conventional a-Si TFT's.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.26-32
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• 2003

Then-channel poly-Si thin-film transistors (poly-Si TFT's) formed by solid phase crystallization (SPC) method on glass were measured to obtain the electrical parameters such as of I-V characteristics, mobility, leakage current, threshold voltage, and subthreshold slope. Then, devices were analyzed to obtain the reliability and appliability on TFT-LCD with large-size and high density. In n-channel poly-Si TFT with 5$\mu\textrm{m}$/2$\mu\textrm{m}$, 8$\mu\textrm{m}$, 30$\mu\textrm{m}$ devices of channel width/length, the field effect mobilities are 111, 116, 125 $\textrm{cm}^2$/V-s and leakage currents are 0.6, 0.1, and 0.02 pA/$\mu\textrm{m}$, respectively. Low threshold voltage and subthreshold slope, and good ON-OFF ratio are shown, as well. Thus. the poly-Si TFT's used by SPC are expected to be applied on TFT-LCD with large-size and high density, which can integrate the display panel and peripheral circuit on a targe glass substrate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04a
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• pp.169-172
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• 2000

A-Si:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly-Si films were achieved by various anneal techniques ; isothermal, RTA, and excimer laser anneal. The TFT on as-grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from $200^{\circ}C$ to $1000^{\circ}C$. The TFT on poly-Si showed an improved $I_{on}/I_{off}$ ratio of $10^6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly-Si TFTs.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.23-30
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• 1993

Hydrogenation on the top gate and bottom gate Poly-Si TET's was performed by using Nh$_{3}$ plasma and annealing SiN film deposited by PECVD and then the electric characteristics on Poly-Si TET were investigated. As the time of NA$_{3}$ plasma treatment increaes, on/off current ratio gradually increases and the swing value decreases. The trap densities of graim boundaries in Poly-Si decrease very much during the inital 20min of hydrogenation time, and the decreasing scale becomes smaller after 20 min. The electric characteristics of the top gate TFT are better than those of the bottom gate TFT, it is considered due to the defects at the interface between the Poly-Si and the underlayer, SiO$_{2}$. After NH$_{3}$ plasma was treated for 2 hours for the top gate TFT, as the aging time atroon temperature increases on current was not scacely changed and off current decreases more than 1 order. Gate current density recovers to original value after the aging treatment for 8 days and then the electric characteristics are finally improved. It is suggested that the degraded characteristics of gate oxide are improved, from the variations of C-V characteristics with aging time. For the hydrogenation of isothermal and isochronal annealing SiN film deposited by PECVD, the characteristics of Poly-Si TFT are improved with increasing annealing temperature and are not largely changed with increasing annealing time. This results is good in agreement with the hydrogen reduction in Sin film as variations of annealing temperature and time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.60-61
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• 2007

In this paper, the p-channel poly Si thin-film transistors (Poly-Si TFT's) using formed by solid phase crystallization (SPC) on glass substrate were fabricated. And we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's to indicate non-volatile memory (NVM) effect. Poly-Si TFT is investigated by measuring the electrical properties of poly-Si films, such as I-V characteristics, on/off current ratio. NVM characteristics is showed by measuring the threshold voltage change of TFT through I-V characteristics.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.126-132
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• 1995

The electrical stress of short channel polycrystalline silicon (poly-Si) thin film transistor (TFT) has been investigated. The device characteristics of short channel poly-Si TFT with 5$\mu$m channel length has been observed to be significantly degraded such as a large shift in threshold voltage and asymmetric phenomena after the electrical stress. The dominant degradation mechanism in long channel poly-Si TFT's with 10$\mu$m and 20$\mu$m channel length respectively is charage trappling in gate oxide while that in short channel device with 5.mu.m channel length is defect creation in active poly-Si layer. We propose that the increased defect density within depletion region near drain junction due to high electric field which could be evidenced by kink effect, constitutes the important reason for this significant degradation in short channel poly-Si TFT. The proposed model is verified by comparing the amounts of the defect creation and the charge trapping from the strechout voltage.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.2031-2033
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• 2005

poly-Si TFT의 kink 전류를 억제하는 L-shaped dual-gate TFT 구조를 제안하고 이를 제작하였다. 제안된 소자는 채널의 그레인 방향을 일정하게 성장시키는 SLS나 CW laser 결정화 방법을 사용한다. L자 모양의 게이트 구조를 사용하여 서고 다른 전계효과 이동도를 갖는 두 개의 sub-TFT를 구현할 수 있으며, 이러한 sub-TFT간의 특성차이가 kink 전류를 억제시킨다. 직접 제작한 L-shaped dual-gate 구조의 소자가 poly-Si TFT의 kink 전류를 억제하고, 전류포화 영역에서 전류량을 고정시킴으로써 신뢰성이 향상됨을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.489-492
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• 1999

The effects of alternate bias stress on p-channel poly-Si TPT's has been systematically investigated. It has been shown that the application of alternate bias stress affects device degradation for the negative bias stress as well as device improvement for the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ under bias stress.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.101-105
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• 2000

The effects of electrical on n-channel offset gated poly-Si TFT's have been investigated. It is observed that the electrical field near the drain region in offset devices is smaller than that of conventional device by simulation results. The variation rate of threshold voltage and subthreshold slope decrease with increasing the offset length because of lowering the electric field near the drain region. The offset gated poly-Si TFT's have been probed effective in reducing the degradation rate of device performance under electrical stressing.

• Proceedings of the Materials Research Society of Korea Conference
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• 1994.11a
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• pp.35-36
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• 1994