• 제목/요약/키워드: Plating Thickness

검색결과 230건 처리시간 0.026초

금속도금공정에서의 최적 모수 값 결정 (Optimum Parameter Values for A Metal Plating Process)

  • 김영진;홍성훈;이민구;권혁무
    • 대한산업공학회지
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    • 제34권3호
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    • pp.337-343
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    • 2008
  • The problem of determining the optimum metal plating thicknesses on the plane and curved surfaces of an electronic part is considered. A lower specification limit for the plating thickness is usually pre-specified. In most applications, the plating thickness on the curved surface is proportional to that on the plane surface. The proportion can be adjusted by adding chemical catalysts to the plating fluid. From the economic point of view, nonconforming items with a thickness smaller than the lower specification limit incur rejection costs, such as rework and scrap costs, while a thicker plating may incur an excessive material costs. In this article, an economic model is proposed for simultaneously determining the target plating thickness and the ratio of the plating thickness on the plane surface to that on the curved surface. An illustrative example demonstrates the applicability of the proposed model.

A Study on the Optimized Copper Electrochemical Plating in Dual Damascene Process

  • Yoo, Hae-Young;Chang, Eui-Goo;Kim, Nam-Hoon
    • Transactions on Electrical and Electronic Materials
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    • 제6권5호
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    • pp.225-228
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    • 2005
  • In this work, we studied the optimized copper thickness in Cu ECP (Electrochemical Plating). In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge (bump, hump or over-plating amount), Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness. In the aspect of bump and dishing, the bulge increased according as target plating thickness decreased. Dishing of edge was larger than center of wafer. Also in case of electrical property, metal line resistance distribution became broad gradually according as Cu ECP thickness decreased. In conclusion, at least $20\%$ reduced Cu ECP thickness from current baseline; $0.8\;{\mu}m$ and $1.0\;{\mu}m$ are suitable to be adopted as newly optimized Cu ECP thickness for local and intermediate layer.

니켈 표면처리공정에서 전류밀도 효과분석 (Effect of Current Density on Nickel Surface Treatment Process)

  • 김용운;정구형;홍인권
    • 공업화학
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    • 제19권2호
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    • pp.228-235
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    • 2008
  • 니켈 표면처리 공정에서 전류밀도에 따라 니켈의 전착두께가 증가되었으며, 증가폭은 $6{\sim}10A/dm^2$에서 저전류보다 높게 나타났다. 전류밀도를 측정하기 위해 Hull-cell 분석을 수행 하였다. 최적 공정온도는 $60^{\circ}C$, pH는 3.5~4.0이었고, 전해용액 중 니켈이온의 농도는 300 g/L 이상에서 농도에 따라 전착두께가 증가되었다. 전류밀도에 따라 용액 중 니켈이온 감소 속도가 증가되었는데, 이는 음극표면에서 니켈 전착 량에 따른 전착두께의 증가를 나타낸다. 그러나 전착속도가 빠를 경우 니켈 전착 층의 치밀성은 저하되며, 표면의 상태는 불규칙하게 변화된다. 니켈이온의 전착과정이 불규칙하게 일어나 조직의 pin hole 등을 야기해 표면특성을 저하시키는 것으로 확인되었다. 광택니켈 전착 후 25 h 내식을 유지한 결과, 낮은 전류밀도를 유지하는 것이 내식특성이 우수한 것으로 나타났다. 프로그램모사 결과, 전류밀도가 높아질수록 확산 층의 두께는 증가하며, 음극표면의 농도는 낮아진다. 농도분포는 낮은 전류밀도에서 고른 분포를 나타내었으며 이는 일정한 전착두께를 예측할 수 있다. 생산성 저하를 예방하기 위해 공정시간은 크게 변화시키지 않았으며, 전류밀도와 전착두께를 변화시키면서 공정변수를 조절하였다. 본 연구의 표면분석 결과 조직특성이나 내식성 등의 표면 물성이 낮은 전류밀도를 사용할 경우에 더욱 우수한 것으로 나타났다.

직조된 SiC 섬유에 무전해 구리도금 시 도금 조건의 영향 (Effect of Plating Conditions on Electroless Copper Plating on SiC Fabric)

  • 이기환;손유한;한태양;이경진;김혜성;한준현
    • 한국표면공학회지
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    • 제50권4호
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    • pp.244-250
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    • 2017
  • Effects of plating conditions (dispersant concentration, plating time, and ultrasonication) on electroless Cu plating on SiC fabric woven by crossing of SiC continuous fibers vertically were studied. The ultrasonic dispersion treatment not only did not improve the dispersion of the SiC fibers, but also did not change the plating thickness. The ultrasonication in the pretreatment step of electroless plating did not improve the dispersion of the fibers, while the ultrasonication in the plating step enhanced the dispersion of the fibers and decreased the thickness of the Cu films. It was possible to control the thickness of the Cu coating layer as well as the dispersion of the fibers in the fabric by changing the plating conditions such as dispersant concentration, plating time, and ultrasonication, but it was very difficult to coat copper on the intersection of vertical fibers in the fabric.

The Effect of Barrel Vibration Intensity to the Plating Thickness Distribution

  • Lee, Jun-Ho;Roselle D. Llido
    • 한국표면공학회:학술대회논문집
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    • 한국표면공학회 1999년도 추계학술발표회 초록집
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    • pp.15-15
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    • 1999
  • In chip plating, several parameters must be taken into consideration. Current density, solution concentration, pH, solution temperature, components volume, chip and media ratio, barrel geometrical shape were most likely found to have an effect to the process yields. The 3 types of barrels utilized in chip plating industry are the conventional rotating barrel. vibrational barrel (vibarrel), and the centrifugal type. Conventional rotating barrel is a close type and is commonly used. The components inside the barrel are circulated by the barrel's rotation at a horizontal axis. Process yield has known to have higher thickness deviation. The vibrational barrel is an open type which offers a wide exposure to electrolyte resulting to a stable thickness deviation. It rotates in a vertical axis coupled with multi-vibration action to facilitate mixed up and easy transportation of components, The centrifugal barrel has its plated work centrifugally compacted against the cathode ring for superior electrical contact with simultaneous rotary motion. This experiment has determined the effect of barrel vibration intensity to the plating thickness distribution. The procedures carried out in the experiment involved the overall plating process., cleaning, rinse, Nickel plating, Tin-Lead plating. Plating time was adjusted to meet the required specification. All other parameters were maintained constant. Two trials were performed to confirm the consistency of the result. The thickness data of the experiment conducted showed that the average mean value obtained from higher vibrational intensity is nearer to the standard mean. The distribution curve shown has a narrower specification limits and it has a reduced variation around the target value, Generally, intensity control in vi-barrel facilitates mixed up and easy transportation of components, However, it is desirable to maintain an optimum vibration intensity to prevent solution intrusion into the chips' internal electrode. A cathodic reaction can occur in the interface of the external and internal electrode. $2HD{\;}+{\;}e{\;}{\rightarrow}20H{\;}+{\;}H_2$ Hydrogen can penetrate into the body and create pressure which can cause cracks. At high intensity, the chip's motion becomes stronger, its contact between each other is delayed and so plating action is being controlled. However, the strong impact created by its collision can damage the external electrode's structure thereby resulting to bad plating condition. 1 lot of chip was divided into two equal partion. Each portion was loaded to the same barrel one after the other. Nickel plating and tin-lead plating was performed in the same station. Portion A maintained the normal barrel vibration intensity and portion B vibration intensity was increased two steps higher. All other parameters, current, solution condition were maintained constant. Generally, plating method find procedures were carried out in a best way to maintained the best plating condition. After plating, samples were taken out from each portion. molded and polished. Plating thickness was investigated for both. To check consistency of results. 2nd trial was done now using different lot of another characteristics.

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Part 25급 항공기용 금속계 제동패드 백플레이트의 표면처리 (Surface Treatment of Backplate for Part 25 Aircraft Metal Brake Pads)

  • 김호형;김민지;김경택
    • 한국항행학회논문지
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    • 제28권4호
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    • pp.544-551
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    • 2024
  • 본 연구에서는 도금 공정 시뮬레이션에 필요한 전기화학적 분극 데이터와 도금 조건 시뮬레이션 및 도금층의 특성 평가에 대해 다루었다. Ni과 Cu의 동전위 분극 분석 및 정전류 분극 시험을 통해 얻은 전기화학적 분극 데이터는 도금액의 유동 조건에 따른 과전압 분포 변화를 관찰하는 데 사용되었다. 도금 조건 시뮬레이션에서는 랙 핀의 접점 위치와 개수가 도금 품질에 미치는 영향을 분석하기 위해 다양한 변수 하에서 전류 밀도 분포 및 도금 두께 분포를 평가하였다. 양극 형상, 극간 거리, 보조 양극 배치, 피도금체 간격 변화 등의 변수에 따른 시뮬레이션 결과를 통해 도금 두께 편차를 개선할 수 있는 방안을 모색하였다. 또한, 도금층의 특성 평가는 버퍼레이어 형성 유무에 따른 도금층의 두께, 밀착성 및 박리 여부를 분석하였다. 시뮬레이션을 통해 도금 공정의 효율성과 품질 향상을 위한 중요한 기초 데이터로 활용될 수 있다.

PCB 및 패키징 공정에서의 도금 시뮬레이션 기술 적용 (Application of Plating Simulation for PCB and Pakaging Process)

  • 이규환
    • 마이크로전자및패키징학회지
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    • 제19권3호
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    • pp.1-7
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    • 2012
  • Electroplating technology is widely used in semiconductor microelectronic industry. With the development of semiconductor integrated circuit to high density and light-small scale, Extremely high quality and plated uniformity of the deposited metals are needed. Simulation technique can help to obtain better plating results. Although a few plating simulation softwares have been commercialized, plating simulation is not widely prevalent in Korea. In this paper, principle of electroplating and mathematical modeling of plating simulation are discussed. Also introduced are some cases enhancing plating thickness uniformity on leadframe, PCB and wafer by using plating simulation.

슈퍼크리티컬 나노 플레이팅에 의한 표면개질 (The Surface Improvement by Supercritical Nano Plating)

  • 김윤해;배창원;김도완;문경만;김동훈;조영대;강병윤
    • 대한기계학회논문집A
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    • 제33권9호
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    • pp.913-921
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    • 2009
  • In this study, supercritical nano plating was performed to observe its effect on materials. Using supercritical carbon dioxide as a solvent, we observed how different pressures and temperatures of the supercritical fluid affected the process and its outcome. The plating current increases as pressure increases from 8 MPa to 16 MPa, but it decreases after that. Similarly, the plating current increases as temperature is increased from $35^{\circ}C$ to $45^{\circ}C$, but the current decreases after that. Also, the thickness of the wet electrolyte plating is about $35\sim50{\mu}m$, while the thickness of the plating done using supercritical fluid is about $20\sim25{\mu}m$. At the results, It to it is considered that supercritical nano plating enable to form more thin and stable plating than wet electroplating methods. Also both of the electroplating methods could be affected plating quality by surface condition, and the supercritical nano plating has been confirmed to product more uniform plating surface than wet electroplating.

Electroplating process for the chip component external electrode

  • Lee, Jun-Ho
    • 한국표면공학회:학술대회논문집
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    • 한국표면공학회 2000년도 추계학술발표회 초록집
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    • pp.1-2
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    • 2000
  • In chip plating, several parameters must be taken into consideration. Current density, solution concentration, pH, solution temperature, components volume, chip and media ratio, barrel geometrical shape were most likely found to have an effect to the process yields. The 3 types of barrels utilized in chip plating industry are the onventional rotating barrel, vibrational barrel(vibarrel), and the centrifugal type. Conventional rotating barrel is a close type and is commonly used. The components inside the barrel are circulated by the barrel's rotation at a horizontal axis. Process yield has known to have higher thickness deviation. The vibrational barrel is an open type which offers a wide exposure to electrolyte resulting to a stable thickness deviation. It rotates in a vertical axis coupled with multi-vibration action to facilitate mixed up and easy transportation of components. The centrifugal barrel has its plated work centrifugally compacted against the cathode ring for superior electrical contact with simultaneous rotary motion. This experiment has determined the effect of barrel vibration intensity to the plating thickness distribution. The procedures carried out in the experiment involved the overall plating process., cleaning, rinse, Nickel plating, Tin-Lead plating. Plating time was adjusted to meet the required specification. All other parameters were maintained constant. Two trials were performed to confirm the consistency of the result. The thickness data of the experiment conducted showed thatbthe average mean value obtained from higher vibrational intensity is nearer to the standard mean. The distribution curve shown has a narrower specification limits and it has a reduced variation around the target value. Generally, intensity control in vi-barrel facilitates mixed up and easy transportation of components. However, it is desirable to maintain an optimum vibration intensity to prevent solution intrusion into the chips' internal electrode. A cathodic reaction can occur in the interface of the external and internal electrode. 2H20 + e $\rightarrow$M/TEX> 20H + H2.. Hydrogen can penetrate into the body and create pressure which can cause cracks. At high intensity, the chip's motion becomes stronger, its contact between each other is delayed and so plating action is being controlled. However, the strong impact created by its collision can damage the external electrode's structure there by resulting to bad plating condition.

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Dual Damascene 공정에서 Bottom-up Gap-fill 메커니즘을 이용한 Cu Plating 두께 최적화 (Cu Plating Thickness Optimization by Bottom-up Gap-fill Mechanism in Dual Damascene Process)

  • 유해영;김남훈;김상용;장의구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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    • pp.93-94
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    • 2005
  • Cu metallization using electrochemical plating(ECP) has played an important role in back end of line(BEOL) interconnect formation. In this work, we studied the optimized copper thickness using Bottom-up Gap-fill in Cu ECP, which is closely related with the pattern dependencies in Cu ECP and Cu dual damascene process at 0.13 ${\mu}m$ technology node. In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge, Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness.

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