• Journal of the Korean Institute of Traditional Landscape Architecture
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• v.30 no.3
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• pp.87-96
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• 2012

This study aimed at empirically identifying how the cultural phenomena of localisation and attachment are implemented through Mohyeonjeong and Supodae at Gajo-myeon, Geochang-gun, Gyeongnam. 'Daehakdong', the name of the place where the Mohyeon-jeong and Supodae is located, has a meaning of the place where Geong-Pil Kim(金宏弼) the Hanhwondang(寒暄堂), one of the 5 eastern sages, and Yeo-Chang Jeong(鄭汝昌) the Ildu tought Neo-Confucianism. In addition, in case of Mt. Odo(1,134m) embracing the garden, the meaning of Odo is the five virtues in Confucianism, so we can see that Confucianism was strong in that area. The meaning of 'Mohyeon(慕賢)', "missing and thinking of sages", reflects the emotion of attachment to the place where people pay a tribute to the memory of Seon-Saeng Yang the Hwondu, one of the 5 eastern sages and the creator of Neo-Confucianism in Kyeongnam, and Suk-Ryang Choi(崔淑梁) the ancestors Pyeongchon. In addition, Odojae(吾道齋), Kijeok monument to pay a tribute to the memory of Pyeongchon, the persimmon tree symbolizing Hanhwondang, and Jidongam(志同巖) standing in front of Mohyeon pavillion represent the united wills of the above 3 people to show their Dohak(道學) spirit by practicing it, and also a reiterated expression of attachment to the place. 'Hwonduyangseonsaeng janggujiso' and 'Pyeongchonchoigong ganghakjiso(坪村崔公講學地所)' engraved on the rock of Myeongso Supodae where they gave a lecture of Neo-Confucianism to local Confucianists for many years and enjoyed nature make us to identify the intrinsic meaning of the location that was inherited in the memory of people. Along with this, most of the content of poetry, restoration records, and Sangryang articles are filled with the content reminding of the historical meaning and origin of Mohyeon-jeong and Supodae, so we can see from this that the place had the spatial meaning of Jangsujiso(藏修之所), 'the place of lecturing and communicating' and respecting ancient sages. This spatial tradition is the result of positive attachment to the place, and Mohyeon-jeong and Supodae is the place where the attachment to the place was made spontaneously througth the localisation. To sum it up, Mohyeon-jeong and Supodae was the place of attachment where one paid a tribute to the memory of ancient sages, and Mohyeonjeong and Supodae rocks were the representative examples of the localisation to show the meaning of the place by implication. Studying the process of attachment and localisation of the place does not only enable us to infer the genuine form of the traditional memorial space and park, but also to reproduce the place with the modern concept.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.12
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• pp.419-428
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• 2022

Since in-place updates for pages are not allowed in flash memory, all new page writes should be written in an out-of-place manner. The old overwritten pages are invalidated. Such invalidated pages eventually trigger the costly garbage collection process. Since the garbage collection causes numerous read and write operations, it is one of the flash memory's major performance issues. In 2R, it modified the garbage collection algorithm, which applies the I/O characteristics of the On-Line Transaction Process workload to improve the Write Amplification Factor. However, this algorithm has a region pollution problem. Therefore, in this paper, we developed 2R++ that additionally separates pages with long access intervals to solve the region pollution problem. 2R++ introduces an extra bit per block to separate warm pages based on a second chance mechanism. Prevents warm pages from being misidentified as cold pages to solve region pollution problem. We conducted the experiments on TPC-C and Linkbench to make the performance comparison. The experiment showed that 2R++ achieved a Write Amplification Factor improvement of 57.8% and 13.8% compared to 2R, respectively.

• International Journal of Internet, Broadcasting and Communication
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• v.13 no.3
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• pp.104-108
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• 2021

In order to improve performance in IoT, edge computing system, a memory is usually configured in a hierarchical structure. Based on the distance from CPU, the access speed slows down in the order of registers, cache memory, main memory, and storage. Similar to the change in performance, energy consumption also increases as the distance from the CPU increases. Therefore, it is important to develop a technique that places frequently used data to the upper memory as much as possible to improve performance and energy consumption. However, the technique should solve the problem of cache performance degradation caused by lack of spatial locality that occurs when the data access stride is large. This study proposes a technique to selectively place data with large data access stride to a software-controlled cache. By using the proposed technique, data spatial locality can be improved by reducing the data access interval, and consequently, the cache performance can be improved.

• Animal cells and systems
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• v.14 no.1
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• pp.11-15
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• 2010

Long-term working memory (LTWM) is a subdivision concept of working memory and indicates the enhancement of performance in a working memory task. LTWM has been shown in humans who have been engaged in a specific task requiring working memory over a long time. However, there is very little understanding of the exact mechanism of LTWM because of limitations of experimental methods in human studies. We have modified the standard T-maze task, which is used to test working memory in mice, to demonstrate LTWM in an animal model. We observed an enhancement of performance by repeated experience with the same working memory load in mice, which can be regarded as an LTWM. This effect seems to depend on the condition wherein a delay was given. This task may be a good experimental protocol to assess LTWM in animal studies.

• Journal of KIISE:Databases
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• v.36 no.5
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• pp.374-385
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• 2009

Flash memory becomes increasingly popular as data storage for various devices because of its versatile features such as non-volatility, light weight, low power consumption, and shock resistance. Flash memory, however, has some distinct characteristics that make today's disk-based database technology unsuitable, such as no in-place update and the asymmetric speed of read and write operations. As a result, most traditional disk-based database systems may not provide the best attainable performance on flash memory. To maximize the database performance on flash memory, some approaches have been proposed where only the changes made to the database, i.e., logs, are written to another empty place that has born erased in advance. In this paper, we propose an efficient log management scheme for flash-based database systems. Unlike the previous approaches, the proposed approach stores logs in specially allocated blocks, called log blocks. By evenly distributing logs across log blocks, the proposed approach can significantly reduce the number of write and erase operations. Our performance evaluation shows that the proposed approaches can improve the overall system performance by reducing the number of write and erase operation compared to the previous ones.

• Journal of the Korean Geographical Society
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• v.44 no.3
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• pp.301-322
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• 2009

This paper is an attempt to explore semiotic representations of subway space as the urban machine space of local mobility in terms of space, time and place. For this, the second section of the paper reviews the contours of the urban space of mobility in terms of 'machine space', 'non-place' and 'cognitive map'. The third section interprets the sings of 'spatial' and 'temporal' representations of subway space in Daegu, and suggests the implications of the semiotic representations. It is uncovered that various sign-scapes which coexist in the subway space in coordinated or contradictory ways product the space into multiple and complex techno-social spaces. That is, the spatio-temporal representations of the subway space form the space of 'non-place' on the one hand and the space of 'place' on the other hand, and involve the spatialization of 'memory' on the one hand and the spatialization of 'forgetting' on the other hand. Thus, the subway space should be regarded to be not only the space of 'mobility' which people move in and through, but also the space of 'identity' which has effects on the ways for them to see the machine space and its urban space.

• Journal of the Korea Society of Computer and Information
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• v.20 no.11
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• pp.1-8
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• 2015

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

• Electrical & Electronic Materials
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• v.13 no.12
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• pp.6-9
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• 2000

Over the years of decades, the memory technology has progressed a long, marble way. As we have evidenced from the Intel's 1Kb DRAM in 1970 to the Gigabit era of 2000's, the road further ahead towards the Terabit era will be unfolded. The technology once perceived inconceivable is in realization today, and similarly roadblocks as we know of today mayvecome trivial issues for tomorrow. For the inquiring mind, the question is how the "puzzle"of tomorrow's memory technology is pieced-in today. The process will take place both in evolutionary and revolutionary ways. Among these, note-worthy are the changes in DRAM architecture and the cell process technology. In this paper, some technical approaches will be discussed to bring these aspects into a general overview and a per-spective with possibilities for the new memory technology will be presented.presented.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.17-20
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• 2000

Over the years of decades, the memory technology has progressed a long, marble way. As we have evidenced from the Intel’s 1Kb DRAM in 1970 to the Gigabit era of 2000’s, the road further ahead towards the Terabit era will be unfolded. The technology once perceived inconceivable is in realization today, and similarly roadblocks as we know of today may become trivial issues for tomorrow. For the inquiring mind, the question is how the “puzzle” of tomorrow’s memory technology is pieced-in today. The process will take place both in evolutionary and revolutionary ways. Among these, note-worthy are the changes in DRAM architecture and the cell process technology. In this paper, some technical approaches will be discussed to bring these aspects into a general overview and a perspective with possibilities for the new memory technology will be presented.

• The KIPS Transactions:PartD
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• v.13D no.3 s.106
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• pp.377-382
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• 2006

Advantageous features of flash memory are stimulating its exploitation in mobile and ubiquitous related devices. The hardware characteristics of flash memory however place restrictions upon this current trend. In this paper, a cleaning policy for flash memory is proposed in order to decrease the necessary penally for recycling of memory minimizing the degradation of performance at the same time. The proposed cleaning algorithm is based on partitioning of candidate memory regions, to be reclaimed as free, into a number of groups. In addition, in order to improve the balanced utilization of the entire flash memory space in terms of 'wearing-out', a free segment selection algorithm is discussed. The impact of the proposed algorithms is evaluated through a number of experiments. Moreover, the composition of the optimal configuration featuring the proposed methods is tested through experiments.