• Journal of IKEEE
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• v.23 no.3
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• pp.941-946
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• 2019

In this paper, the author analyzed the PCI (Physical Cell Identification) allocation methods in the LTE (Long Term Evolution) SON (Self Organization Network) environment. A variety of techniques have been proposed for how to allocate PCI, and the LTE standard fundamentally explained that collision between a cell and neighbor cells arise while a cell assign the PCI. Therefore, in this paper, the author examined the scenarios of PCI collision, weak collision, and confusion proposed by LTE specification. In addition, the cell central approach and the distributed approach were discussed as solutions for each scenario. In this paper, the author reviewed the approach of graphic coloring technique which was studied recently and explained the strategy of central approach.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.369-378
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• 2003

This paper presents design and VLSI implementations of a reassembly processor for ATM/AAL. The assembly processor is responsible for processing ATM cells from the receive physical interface. It controls the transfer of the AAL payload to host memory and performs all necessary SAR and CPCS checks. We propose the improved structure of cell identification algorithm and smart scatter method for host memory management. The proposed cell identification algorithm quickly locates the appropriate reassembly VC table based on the received VPI./VCI channel value in the ATM header. The cell identification algorithm also allow complete freedom in assignment of VCI/VPI values. The reassembly processor uses a smart scatter method to write cell payload data to host memory. It maintains the scatter operation and controls the incoming DMA block during scatter DMA to host memory. The proposed reassembly processor can perform reassembly checks on AAL. OAM cell. For an AAL5 connection, only CPCS checks, including the CRC32, are performed. In this paper, we proposed a practical reassembly architecture. The design of reassembly processor has become feasible using 0.6${\mu}{\textrm}{m}$ CMOS gate array technology.